
Linh M. Nguyen
Examiner (ID: 16124)
| Most Active Art Unit | 2816 |
| Art Unit(s) | 3992, 2816, 2857 |
| Total Applications | 1009 |
| Issued Applications | 920 |
| Pending Applications | 36 |
| Abandoned Applications | 53 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1421613
[patent_doc_number] => 06525586
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-02-25
[patent_title] => 'Programmable delay element using differential technique'
[patent_app_type] => B1
[patent_app_number] => 09/986640
[patent_app_country] => US
[patent_app_date] => 2001-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 3694
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/525/06525586.pdf
[firstpage_image] =>[orig_patent_app_number] => 09986640
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/986640 | Programmable delay element using differential technique | Nov 8, 2001 | Issued |
Array
(
[id] => 5901916
[patent_doc_number] => 20020140465
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-10-03
[patent_title] => 'Output circuit'
[patent_app_type] => new
[patent_app_number] => 10/052981
[patent_app_country] => US
[patent_app_date] => 2001-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 6893
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0140/20020140465.pdf
[firstpage_image] =>[orig_patent_app_number] => 10052981
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/052981 | Output circuit | Nov 7, 2001 | Issued |
Array
(
[id] => 1161113
[patent_doc_number] => 06762631
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-07-13
[patent_title] => 'Lock detection circuit for a phase locked loop circuit'
[patent_app_type] => B1
[patent_app_number] => 09/992950
[patent_app_country] => US
[patent_app_date] => 2001-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 4959
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/762/06762631.pdf
[firstpage_image] =>[orig_patent_app_number] => 09992950
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/992950 | Lock detection circuit for a phase locked loop circuit | Nov 5, 2001 | Issued |
Array
(
[id] => 1317127
[patent_doc_number] => 06611161
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-08-26
[patent_title] => 'Charge pump circuit for a high speed phase locked loop'
[patent_app_type] => B1
[patent_app_number] => 09/993283
[patent_app_country] => US
[patent_app_date] => 2001-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4186
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/611/06611161.pdf
[firstpage_image] =>[orig_patent_app_number] => 09993283
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/993283 | Charge pump circuit for a high speed phase locked loop | Nov 5, 2001 | Issued |
Array
(
[id] => 6790401
[patent_doc_number] => 20030085745
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-05-08
[patent_title] => 'PMOS/NMOS circuits'
[patent_app_type] => new
[patent_app_number] => 10/008532
[patent_app_country] => US
[patent_app_date] => 2001-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 1068
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 27
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0085/20030085745.pdf
[firstpage_image] =>[orig_patent_app_number] => 10008532
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/008532 | PMOS/NMOS circuits | Nov 4, 2001 | Abandoned |
Array
(
[id] => 1226229
[patent_doc_number] => 06700425
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-03-02
[patent_title] => 'Multi-phase clock generators that utilize differential signals to achieve reduced setup and hold times'
[patent_app_type] => B1
[patent_app_number] => 10/017628
[patent_app_country] => US
[patent_app_date] => 2001-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 11
[patent_no_of_words] => 9648
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/700/06700425.pdf
[firstpage_image] =>[orig_patent_app_number] => 10017628
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/017628 | Multi-phase clock generators that utilize differential signals to achieve reduced setup and hold times | Oct 29, 2001 | Issued |
Array
(
[id] => 1022840
[patent_doc_number] => 06888379
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-05-03
[patent_title] => 'Phase comparator circuit'
[patent_app_type] => utility
[patent_app_number] => 10/088205
[patent_app_country] => US
[patent_app_date] => 2001-10-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 15
[patent_no_of_words] => 9128
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/888/06888379.pdf
[firstpage_image] =>[orig_patent_app_number] => 10088205
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/088205 | Phase comparator circuit | Oct 10, 2001 | Issued |
Array
(
[id] => 1285620
[patent_doc_number] => 06642766
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-11-04
[patent_title] => 'Digital circuit, LSI including the same and method for removing noise'
[patent_app_type] => B2
[patent_app_number] => 09/973887
[patent_app_country] => US
[patent_app_date] => 2001-10-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 3029
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/642/06642766.pdf
[firstpage_image] =>[orig_patent_app_number] => 09973887
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/973887 | Digital circuit, LSI including the same and method for removing noise | Oct 10, 2001 | Issued |
Array
(
[id] => 979518
[patent_doc_number] => 06930524
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-08-16
[patent_title] => 'Dual-phase delay-locked loop circuit and method'
[patent_app_type] => utility
[patent_app_number] => 09/974386
[patent_app_country] => US
[patent_app_date] => 2001-10-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 6888
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 255
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/930/06930524.pdf
[firstpage_image] =>[orig_patent_app_number] => 09974386
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/974386 | Dual-phase delay-locked loop circuit and method | Oct 8, 2001 | Issued |
Array
(
[id] => 5933970
[patent_doc_number] => 20020060585
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-05-23
[patent_title] => 'Redundant comparator design for improved offset voltage and single event effects hardness'
[patent_app_type] => new
[patent_app_number] => 09/973106
[patent_app_country] => US
[patent_app_date] => 2001-10-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1758
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0060/20020060585.pdf
[firstpage_image] =>[orig_patent_app_number] => 09973106
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/973106 | Redundant comparator design for improved offset voltage and single event effects hardness | Oct 8, 2001 | Issued |
Array
(
[id] => 1571654
[patent_doc_number] => 06498520
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-12-24
[patent_title] => 'Minimizing the effect of clock skew in precharge circuit'
[patent_app_type] => B1
[patent_app_number] => 09/973326
[patent_app_country] => US
[patent_app_date] => 2001-10-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 4773
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/498/06498520.pdf
[firstpage_image] =>[orig_patent_app_number] => 09973326
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/973326 | Minimizing the effect of clock skew in precharge circuit | Oct 8, 2001 | Issued |
Array
(
[id] => 1322581
[patent_doc_number] => 06605969
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-08-12
[patent_title] => 'Method and circuit for adjusting the timing of ouput data based on an operational mode of output drivers'
[patent_app_type] => B2
[patent_app_number] => 09/974322
[patent_app_country] => US
[patent_app_date] => 2001-10-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 8376
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/605/06605969.pdf
[firstpage_image] =>[orig_patent_app_number] => 09974322
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/974322 | Method and circuit for adjusting the timing of ouput data based on an operational mode of output drivers | Oct 8, 2001 | Issued |
Array
(
[id] => 1394933
[patent_doc_number] => 06552588
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-04-22
[patent_title] => 'Method and apparatus to generate pseudo-random non-periodic digital sequences'
[patent_app_type] => B1
[patent_app_number] => 09/972140
[patent_app_country] => US
[patent_app_date] => 2001-10-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 2837
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/552/06552588.pdf
[firstpage_image] =>[orig_patent_app_number] => 09972140
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/972140 | Method and apparatus to generate pseudo-random non-periodic digital sequences | Oct 4, 2001 | Issued |
Array
(
[id] => 1519546
[patent_doc_number] => 06501308
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-12-31
[patent_title] => 'Generation of clock signals for a semiconductor memory that are edge-synchronous with the output signals of a clock generator'
[patent_app_type] => B2
[patent_app_number] => 09/972217
[patent_app_country] => US
[patent_app_date] => 2001-10-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 3
[patent_no_of_words] => 2634
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 178
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/501/06501308.pdf
[firstpage_image] =>[orig_patent_app_number] => 09972217
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/972217 | Generation of clock signals for a semiconductor memory that are edge-synchronous with the output signals of a clock generator | Oct 4, 2001 | Issued |
Array
(
[id] => 1177052
[patent_doc_number] => 06750684
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-06-15
[patent_title] => 'Input circuit buffer supporting a low voltage interface and a general low voltage transistor logic(LVVTL) interface'
[patent_app_type] => B2
[patent_app_number] => 09/971991
[patent_app_country] => US
[patent_app_date] => 2001-10-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 11
[patent_no_of_words] => 5696
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/750/06750684.pdf
[firstpage_image] =>[orig_patent_app_number] => 09971991
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/971991 | Input circuit buffer supporting a low voltage interface and a general low voltage transistor logic(LVVTL) interface | Oct 3, 2001 | Issued |
Array
(
[id] => 1022845
[patent_doc_number] => 06888381
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-05-03
[patent_title] => 'High speed peak amplitude comparator'
[patent_app_type] => utility
[patent_app_number] => 09/969837
[patent_app_country] => US
[patent_app_date] => 2001-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 2483
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/888/06888381.pdf
[firstpage_image] =>[orig_patent_app_number] => 09969837
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/969837 | High speed peak amplitude comparator | Sep 30, 2001 | Issued |
Array
(
[id] => 1387545
[patent_doc_number] => 06559691
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-05-06
[patent_title] => 'Voltage level converting circuit'
[patent_app_type] => B2
[patent_app_number] => 09/966086
[patent_app_country] => US
[patent_app_date] => 2001-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5897
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 236
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/559/06559691.pdf
[firstpage_image] =>[orig_patent_app_number] => 09966086
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/966086 | Voltage level converting circuit | Sep 30, 2001 | Issued |
Array
(
[id] => 1394826
[patent_doc_number] => 06552582
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-04-22
[patent_title] => 'Source follower for low voltage differential signaling'
[patent_app_type] => B1
[patent_app_number] => 09/966388
[patent_app_country] => US
[patent_app_date] => 2001-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3109
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/552/06552582.pdf
[firstpage_image] =>[orig_patent_app_number] => 09966388
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/966388 | Source follower for low voltage differential signaling | Sep 26, 2001 | Issued |
Array
(
[id] => 6579949
[patent_doc_number] => 20020041194
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-04-11
[patent_title] => 'Semiconductor integrated circuit having output buffer'
[patent_app_type] => new
[patent_app_number] => 09/965951
[patent_app_country] => US
[patent_app_date] => 2001-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 9302
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0041/20020041194.pdf
[firstpage_image] =>[orig_patent_app_number] => 09965951
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/965951 | Semiconductor integrated circuit having output buffer | Sep 26, 2001 | Issued |
Array
(
[id] => 6092665
[patent_doc_number] => 20020050841
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-05-02
[patent_title] => 'Circuit configuration for detecting the state of at least one electrical actuating element'
[patent_app_type] => new
[patent_app_number] => 09/965487
[patent_app_country] => US
[patent_app_date] => 2001-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3044
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 217
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0050/20020050841.pdf
[firstpage_image] =>[orig_patent_app_number] => 09965487
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/965487 | Circuit configuration for detecting the state of at least one electrical actuating element | Sep 26, 2001 | Issued |