Search

Linh M. Nguyen

Examiner (ID: 16124)

Most Active Art Unit
2816
Art Unit(s)
3992, 2816, 2857
Total Applications
1009
Issued Applications
920
Pending Applications
36
Abandoned Applications
53

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5997695 [patent_doc_number] => 20020027476 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-07 [patent_title] => 'Current amplifier' [patent_app_type] => new [patent_app_number] => 09/945320 [patent_app_country] => US [patent_app_date] => 2001-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3332 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20020027476.pdf [firstpage_image] =>[orig_patent_app_number] => 09945320 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/945320
Current amplifier Aug 30, 2001 Issued
Array ( [id] => 1502864 [patent_doc_number] => 06486719 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-26 [patent_title] => 'Flip-flop circuits having digital-to-time conversion latches therein' [patent_app_type] => B2 [patent_app_number] => 09/935096 [patent_app_country] => US [patent_app_date] => 2001-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 24 [patent_no_of_words] => 7356 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/486/06486719.pdf [firstpage_image] =>[orig_patent_app_number] => 09935096 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/935096
Flip-flop circuits having digital-to-time conversion latches therein Aug 21, 2001 Issued
Array ( [id] => 1510131 [patent_doc_number] => 06441658 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Method and apparatus for vertically locking input and output signals' [patent_app_type] => B1 [patent_app_number] => 09/930749 [patent_app_country] => US [patent_app_date] => 2001-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 10917 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/441/06441658.pdf [firstpage_image] =>[orig_patent_app_number] => 09930749 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/930749
Method and apparatus for vertically locking input and output signals Aug 13, 2001 Issued
Array ( [id] => 1389605 [patent_doc_number] => 06556051 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-29 [patent_title] => 'Apparatus for providing both supports including synchronous dynamic random access memory (SDRAM) module and double data rate (DDR) DRAM module' [patent_app_type] => B2 [patent_app_number] => 09/930797 [patent_app_country] => US [patent_app_date] => 2001-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2673 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/556/06556051.pdf [firstpage_image] =>[orig_patent_app_number] => 09930797 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/930797
Apparatus for providing both supports including synchronous dynamic random access memory (SDRAM) module and double data rate (DDR) DRAM module Aug 13, 2001 Issued
Array ( [id] => 6350301 [patent_doc_number] => 20020057113 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-16 [patent_title] => 'Phase detector' [patent_app_type] => new [patent_app_number] => 09/928807 [patent_app_country] => US [patent_app_date] => 2001-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1633 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20020057113.pdf [firstpage_image] =>[orig_patent_app_number] => 09928807 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/928807
Phase detector Aug 12, 2001 Abandoned
Array ( [id] => 6480125 [patent_doc_number] => 20020024369 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-28 [patent_title] => 'Method for increasing the cut-off frequency in flip-flops' [patent_app_type] => new [patent_app_number] => 09/925904 [patent_app_country] => US [patent_app_date] => 2001-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2476 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20020024369.pdf [firstpage_image] =>[orig_patent_app_number] => 09925904 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/925904
Flip-flop circuit arrangement with increased cut-off frequency Aug 8, 2001 Issued
Array ( [id] => 6933581 [patent_doc_number] => 20010054925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-27 [patent_title] => 'Low-power low-jitter variable delay timing circuit' [patent_app_type] => new [patent_app_number] => 09/925753 [patent_app_country] => US [patent_app_date] => 2001-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5448 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20010054925.pdf [firstpage_image] =>[orig_patent_app_number] => 09925753 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/925753
Low-power low-jitter variable delay timing circuit Aug 8, 2001 Issued
Array ( [id] => 1246959 [patent_doc_number] => 06677799 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-13 [patent_title] => 'Integrator with high gain and fast transient response' [patent_app_type] => B1 [patent_app_number] => 09/925074 [patent_app_country] => US [patent_app_date] => 2001-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2724 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/677/06677799.pdf [firstpage_image] =>[orig_patent_app_number] => 09925074 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/925074
Integrator with high gain and fast transient response Aug 7, 2001 Issued
Array ( [id] => 6029539 [patent_doc_number] => 20020017930 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-14 [patent_title] => 'Signal transmission device' [patent_app_type] => new [patent_app_number] => 09/923950 [patent_app_country] => US [patent_app_date] => 2001-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3464 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20020017930.pdf [firstpage_image] =>[orig_patent_app_number] => 09923950 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/923950
Signal transmission device Aug 7, 2001 Issued
Array ( [id] => 1452997 [patent_doc_number] => 06456141 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Current pulse receiving circuit' [patent_app_type] => B1 [patent_app_number] => 09/922764 [patent_app_country] => US [patent_app_date] => 2001-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 15381 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/456/06456141.pdf [firstpage_image] =>[orig_patent_app_number] => 09922764 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/922764
Current pulse receiving circuit Aug 6, 2001 Issued
Array ( [id] => 6029515 [patent_doc_number] => 20020017926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-14 [patent_title] => 'Frequency determination circuit for a data processing unit' [patent_app_type] => new [patent_app_number] => 09/920867 [patent_app_country] => US [patent_app_date] => 2001-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5497 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20020017926.pdf [firstpage_image] =>[orig_patent_app_number] => 09920867 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/920867
Frequency determination circuit for a data processing unit Aug 2, 2001 Abandoned
Array ( [id] => 1603416 [patent_doc_number] => 06433598 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Process, voltage and temperature independent clock tree deskew circuitry-active drive method' [patent_app_type] => B1 [patent_app_number] => 09/915237 [patent_app_country] => US [patent_app_date] => 2001-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9044 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/433/06433598.pdf [firstpage_image] =>[orig_patent_app_number] => 09915237 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/915237
Process, voltage and temperature independent clock tree deskew circuitry-active drive method Jul 24, 2001 Issued
Array ( [id] => 1425690 [patent_doc_number] => 06507222 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-14 [patent_title] => 'High speed single ended sense amplifier' [patent_app_type] => B1 [patent_app_number] => 09/911334 [patent_app_country] => US [patent_app_date] => 2001-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1904 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/507/06507222.pdf [firstpage_image] =>[orig_patent_app_number] => 09911334 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/911334
High speed single ended sense amplifier Jul 22, 2001 Issued
Array ( [id] => 1129068 [patent_doc_number] => 06791385 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-14 [patent_title] => 'Clock controlling method and circuit' [patent_app_type] => B2 [patent_app_number] => 09/910117 [patent_app_country] => US [patent_app_date] => 2001-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 32 [patent_no_of_words] => 14142 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/791/06791385.pdf [firstpage_image] =>[orig_patent_app_number] => 09910117 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/910117
Clock controlling method and circuit Jul 19, 2001 Issued
Array ( [id] => 7643335 [patent_doc_number] => 06429707 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Reference signal switchover clock output controller' [patent_app_type] => B1 [patent_app_number] => 09/911642 [patent_app_country] => US [patent_app_date] => 2001-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2579 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/429/06429707.pdf [firstpage_image] =>[orig_patent_app_number] => 09911642 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/911642
Reference signal switchover clock output controller Jul 18, 2001 Issued
Array ( [id] => 7635881 [patent_doc_number] => 06380779 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-30 [patent_title] => 'Edge-triggered, self-resetting pulse generator' [patent_app_type] => B1 [patent_app_number] => 09/903927 [patent_app_country] => US [patent_app_date] => 2001-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2667 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 9 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/380/06380779.pdf [firstpage_image] =>[orig_patent_app_number] => 09903927 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/903927
Edge-triggered, self-resetting pulse generator Jul 11, 2001 Issued
Array ( [id] => 1497978 [patent_doc_number] => 06404263 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Mixer having compensation for harmonics of local oscillator signal' [patent_app_type] => B1 [patent_app_number] => 09/903283 [patent_app_country] => US [patent_app_date] => 2001-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2378 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/404/06404263.pdf [firstpage_image] =>[orig_patent_app_number] => 09903283 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/903283
Mixer having compensation for harmonics of local oscillator signal Jul 10, 2001 Issued
Array ( [id] => 6301715 [patent_doc_number] => 20020093370 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-18 [patent_title] => 'Delay circuit using current source' [patent_app_type] => new [patent_app_number] => 09/899626 [patent_app_country] => US [patent_app_date] => 2001-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2523 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20020093370.pdf [firstpage_image] =>[orig_patent_app_number] => 09899626 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/899626
Delay circuit using current source Jul 4, 2001 Issued
Array ( [id] => 1367291 [patent_doc_number] => 06573777 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-03 [patent_title] => 'Variable-delay element with an inverter and a digitally adjustable resistor' [patent_app_type] => B2 [patent_app_number] => 09/893870 [patent_app_country] => US [patent_app_date] => 2001-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4637 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/573/06573777.pdf [firstpage_image] =>[orig_patent_app_number] => 09893870 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/893870
Variable-delay element with an inverter and a digitally adjustable resistor Jun 28, 2001 Issued
Array ( [id] => 1403318 [patent_doc_number] => 06545521 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-08 [patent_title] => 'Low skew, power sequence independent CMOS receiver device' [patent_app_type] => B2 [patent_app_number] => 09/895778 [patent_app_country] => US [patent_app_date] => 2001-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4643 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/545/06545521.pdf [firstpage_image] =>[orig_patent_app_number] => 09895778 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/895778
Low skew, power sequence independent CMOS receiver device Jun 28, 2001 Issued
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