Search

Linh M. Nguyen

Examiner (ID: 16124)

Most Active Art Unit
2816
Art Unit(s)
3992, 2816, 2857
Total Applications
1009
Issued Applications
920
Pending Applications
36
Abandoned Applications
53

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7619580 [patent_doc_number] => 06943606 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-13 [patent_title] => 'Phase interpolator to interpolate between a plurality of clock phases' [patent_app_type] => utility [patent_app_number] => 09/891466 [patent_app_country] => US [patent_app_date] => 2001-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2311 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/943/06943606.pdf [firstpage_image] =>[orig_patent_app_number] => 09891466 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/891466
Phase interpolator to interpolate between a plurality of clock phases Jun 26, 2001 Issued
Array ( [id] => 1462168 [patent_doc_number] => 06392455 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Baud rate generator with fractional divider' [patent_app_type] => B1 [patent_app_number] => 09/881003 [patent_app_country] => US [patent_app_date] => 2001-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3283 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/392/06392455.pdf [firstpage_image] =>[orig_patent_app_number] => 09881003 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/881003
Baud rate generator with fractional divider Jun 13, 2001 Issued
Array ( [id] => 1198165 [patent_doc_number] => 06727738 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-27 [patent_title] => 'Configuration for generating a clock including a delay circuit and method thereof' [patent_app_type] => B2 [patent_app_number] => 09/877027 [patent_app_country] => US [patent_app_date] => 2001-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 35 [patent_no_of_words] => 9216 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/727/06727738.pdf [firstpage_image] =>[orig_patent_app_number] => 09877027 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/877027
Configuration for generating a clock including a delay circuit and method thereof Jun 10, 2001 Issued
Array ( [id] => 6368161 [patent_doc_number] => 20020118006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-29 [patent_title] => 'Phase frequency detector' [patent_app_type] => new [patent_app_number] => 09/873895 [patent_app_country] => US [patent_app_date] => 2001-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 16935 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0118/20020118006.pdf [firstpage_image] =>[orig_patent_app_number] => 09873895 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/873895
Phase frequency detector Jun 3, 2001 Abandoned
Array ( [id] => 7645052 [patent_doc_number] => 06472921 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-29 [patent_title] => 'Delivering a fine delay stage for a delay locked loop' [patent_app_type] => B1 [patent_app_number] => 09/871855 [patent_app_country] => US [patent_app_date] => 2001-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 2831 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/472/06472921.pdf [firstpage_image] =>[orig_patent_app_number] => 09871855 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/871855
Delivering a fine delay stage for a delay locked loop May 30, 2001 Issued
Array ( [id] => 6388794 [patent_doc_number] => 20020180488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-05 [patent_title] => 'FREQUENCY COMPARISON CIRCUIT' [patent_app_type] => new [patent_app_number] => 09/734451 [patent_app_country] => US [patent_app_date] => 2001-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10561 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20020180488.pdf [firstpage_image] =>[orig_patent_app_number] => 09734451 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/734451
Frequency comparison circuit May 29, 2001 Issued
Array ( [id] => 1452952 [patent_doc_number] => 06456126 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Frequency doubler with polarity control' [patent_app_type] => B1 [patent_app_number] => 09/865871 [patent_app_country] => US [patent_app_date] => 2001-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 19 [patent_no_of_words] => 3533 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/456/06456126.pdf [firstpage_image] =>[orig_patent_app_number] => 09865871 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/865871
Frequency doubler with polarity control May 24, 2001 Issued
Array ( [id] => 6430489 [patent_doc_number] => 20020175723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-28 [patent_title] => 'Low voltage charge pump for use in a phase locked loop' [patent_app_type] => new [patent_app_number] => 09/865610 [patent_app_country] => US [patent_app_date] => 2001-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5221 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20020175723.pdf [firstpage_image] =>[orig_patent_app_number] => 09865610 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/865610
Low voltage charge pump for use in a phase locked loop May 24, 2001 Issued
Array ( [id] => 1441312 [patent_doc_number] => 06496046 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-17 [patent_title] => 'Method for increasing the control bandwidth of a frequency control circuit' [patent_app_type] => B2 [patent_app_number] => 09/841802 [patent_app_country] => US [patent_app_date] => 2001-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6562 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/496/06496046.pdf [firstpage_image] =>[orig_patent_app_number] => 09841802 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/841802
Method for increasing the control bandwidth of a frequency control circuit Apr 23, 2001 Issued
Array ( [id] => 1548284 [patent_doc_number] => 06445227 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Rational frequency divider' [patent_app_type] => B1 [patent_app_number] => 09/762451 [patent_app_country] => US [patent_app_date] => 2001-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2395 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/445/06445227.pdf [firstpage_image] =>[orig_patent_app_number] => 09762451 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/762451
Rational frequency divider Apr 12, 2001 Issued
Array ( [id] => 6462027 [patent_doc_number] => 20020021158 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-21 [patent_title] => 'COMPARATOR FOR DETERMINING PROCESS VARIATIONS' [patent_app_type] => new [patent_app_number] => 09/828256 [patent_app_country] => US [patent_app_date] => 2001-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5812 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0021/20020021158.pdf [firstpage_image] =>[orig_patent_app_number] => 09828256 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/828256
Comparator for determining process variations Apr 5, 2001 Issued
Array ( [id] => 722034 [patent_doc_number] => 07055125 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-30 [patent_title] => 'Depopulated programmable logic array' [patent_app_type] => utility [patent_app_number] => 09/827015 [patent_app_country] => US [patent_app_date] => 2001-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 5731 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/055/07055125.pdf [firstpage_image] =>[orig_patent_app_number] => 09827015 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/827015
Depopulated programmable logic array Apr 4, 2001 Issued
Array ( [id] => 1348970 [patent_doc_number] => 06598215 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-22 [patent_title] => 'Datapath design methodology and routing apparatus' [patent_app_type] => B2 [patent_app_number] => 09/820864 [patent_app_country] => US [patent_app_date] => 2001-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8355 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/598/06598215.pdf [firstpage_image] =>[orig_patent_app_number] => 09820864 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/820864
Datapath design methodology and routing apparatus Mar 29, 2001 Issued
Array ( [id] => 1598463 [patent_doc_number] => 06492852 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-10 [patent_title] => 'Pre-divider architecture for low power in a digital delay locked loop' [patent_app_type] => B2 [patent_app_number] => 09/823152 [patent_app_country] => US [patent_app_date] => 2001-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4248 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/492/06492852.pdf [firstpage_image] =>[orig_patent_app_number] => 09823152 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/823152
Pre-divider architecture for low power in a digital delay locked loop Mar 29, 2001 Issued
Array ( [id] => 5901929 [patent_doc_number] => 20020140469 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-03 [patent_title] => 'Low injection charge pump' [patent_app_type] => new [patent_app_number] => 09/819626 [patent_app_country] => US [patent_app_date] => 2001-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1802 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20020140469.pdf [firstpage_image] =>[orig_patent_app_number] => 09819626 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/819626
Low injection charge pump Mar 28, 2001 Issued
Array ( [id] => 1569199 [patent_doc_number] => 06377104 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-04-23 [patent_title] => 'Static clock pulse generator and display' [patent_app_type] => B2 [patent_app_number] => 09/819944 [patent_app_country] => US [patent_app_date] => 2001-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 5975 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/377/06377104.pdf [firstpage_image] =>[orig_patent_app_number] => 09819944 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/819944
Static clock pulse generator and display Mar 27, 2001 Issued
Array ( [id] => 1535067 [patent_doc_number] => 06411134 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-25 [patent_title] => 'Spike-free clock switching' [patent_app_type] => B1 [patent_app_number] => 09/806104 [patent_app_country] => US [patent_app_date] => 2001-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1584 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 480 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/411/06411134.pdf [firstpage_image] =>[orig_patent_app_number] => 09806104 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/806104
Spike-free clock switching Mar 27, 2001 Issued
Array ( [id] => 6115728 [patent_doc_number] => 20020174411 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-21 [patent_title] => 'PROGRAMMING PROGRAMMABLE LOGIC DEVICES USING HIDDEN SWITCHES' [patent_app_type] => new [patent_app_number] => 09/818257 [patent_app_country] => US [patent_app_date] => 2001-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3430 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20020174411.pdf [firstpage_image] =>[orig_patent_app_number] => 09818257 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/818257
Programming programmable logic devices using hidden switches Mar 26, 2001 Issued
Array ( [id] => 6245556 [patent_doc_number] => 20020046388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-18 [patent_title] => 'Semiconductor integrated circuitry' [patent_app_type] => new [patent_app_number] => 09/814868 [patent_app_country] => US [patent_app_date] => 2001-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9071 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20020046388.pdf [firstpage_image] =>[orig_patent_app_number] => 09814868 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/814868
Semiconductor integrated circuitry Mar 22, 2001 Issued
Array ( [id] => 1319583 [patent_doc_number] => 06618848 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-09 [patent_title] => 'Method for designing circuit layout of non-neighboring metal bit lines to reduce coupling effect' [patent_app_type] => B2 [patent_app_number] => 09/814409 [patent_app_country] => US [patent_app_date] => 2001-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2673 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/618/06618848.pdf [firstpage_image] =>[orig_patent_app_number] => 09814409 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/814409
Method for designing circuit layout of non-neighboring metal bit lines to reduce coupling effect Mar 21, 2001 Issued
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