Search

Linh M. Nguyen

Examiner (ID: 16124)

Most Active Art Unit
2816
Art Unit(s)
3992, 2816, 2857
Total Applications
1009
Issued Applications
920
Pending Applications
36
Abandoned Applications
53

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1423101 [patent_doc_number] => 06509775 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-01-21 [patent_title] => 'Synchronous delay circuit and semiconductor integrated circuit apparatus' [patent_app_type] => B2 [patent_app_number] => 09/799543 [patent_app_country] => US [patent_app_date] => 2001-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 8210 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/509/06509775.pdf [firstpage_image] =>[orig_patent_app_number] => 09799543 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/799543
Synchronous delay circuit and semiconductor integrated circuit apparatus Mar 4, 2001 Issued
Array ( [id] => 6998768 [patent_doc_number] => 20010052808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-20 [patent_title] => 'Clock generation circuit generating internal clock of small variation in phase difference from external clock, and semiconductor memory device including such clock generation circuit' [patent_app_type] => new [patent_app_number] => 09/793999 [patent_app_country] => US [patent_app_date] => 2001-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 12086 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20010052808.pdf [firstpage_image] =>[orig_patent_app_number] => 09793999 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/793999
Clock generation circuit generating internal clock of small variation in phase difference from external clock, and semiconductor memory device including such clock generation circuit Feb 27, 2001 Issued
Array ( [id] => 6397189 [patent_doc_number] => 20020036521 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-28 [patent_title] => 'Semiconductor integrated circuit and semiconductor integrated circuit system' [patent_app_type] => new [patent_app_number] => 09/794028 [patent_app_country] => US [patent_app_date] => 2001-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8591 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20020036521.pdf [firstpage_image] =>[orig_patent_app_number] => 09794028 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/794028
Semiconductor integrated circuit and semiconductor integrated circuit system Feb 27, 2001 Issued
Array ( [id] => 1423315 [patent_doc_number] => 06522185 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-02-18 [patent_title] => 'Variable delay CMOS circuit with PVT control' [patent_app_type] => B2 [patent_app_number] => 09/796306 [patent_app_country] => US [patent_app_date] => 2001-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 3995 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/522/06522185.pdf [firstpage_image] =>[orig_patent_app_number] => 09796306 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/796306
Variable delay CMOS circuit with PVT control Feb 27, 2001 Issued
Array ( [id] => 1597862 [patent_doc_number] => 06384649 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Apparatus and method for clock skew measurement' [patent_app_type] => B1 [patent_app_number] => 09/791150 [patent_app_country] => US [patent_app_date] => 2001-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2897 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/384/06384649.pdf [firstpage_image] =>[orig_patent_app_number] => 09791150 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/791150
Apparatus and method for clock skew measurement Feb 21, 2001 Issued
Array ( [id] => 1597964 [patent_doc_number] => 06384676 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-05-07 [patent_title] => 'Signal processing semiconductor integrated circuit device' [patent_app_type] => B2 [patent_app_number] => 09/789566 [patent_app_country] => US [patent_app_date] => 2001-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 11438 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/384/06384676.pdf [firstpage_image] =>[orig_patent_app_number] => 09789566 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/789566
Signal processing semiconductor integrated circuit device Feb 21, 2001 Issued
Array ( [id] => 6527090 [patent_doc_number] => 20020109534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-15 [patent_title] => 'HIGH-SPEED OUTPUT DRIVER' [patent_app_type] => new [patent_app_number] => 09/784769 [patent_app_country] => US [patent_app_date] => 2001-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3645 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20020109534.pdf [firstpage_image] =>[orig_patent_app_number] => 09784769 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/784769
High-speed output driver Feb 14, 2001 Issued
Array ( [id] => 6947209 [patent_doc_number] => 20010020855 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-13 [patent_title] => 'Fast signal selector' [patent_app_type] => new [patent_app_number] => 09/778535 [patent_app_country] => US [patent_app_date] => 2001-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2391 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0020/20010020855.pdf [firstpage_image] =>[orig_patent_app_number] => 09778535 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/778535
Fast signal selector Feb 6, 2001 Abandoned
Array ( [id] => 660120 [patent_doc_number] => 07106114 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-12 [patent_title] => 'Delay time adjusting method of delaying a phase of an output signal until a phase difference between an input signal and the output signal becomes an integral number of periods other than zero' [patent_app_type] => utility [patent_app_number] => 09/777897 [patent_app_country] => US [patent_app_date] => 2001-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 6997 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/106/07106114.pdf [firstpage_image] =>[orig_patent_app_number] => 09777897 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/777897
Delay time adjusting method of delaying a phase of an output signal until a phase difference between an input signal and the output signal becomes an integral number of periods other than zero Feb 6, 2001 Issued
Array ( [id] => 1472308 [patent_doc_number] => 06407627 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-18 [patent_title] => 'Tunable sallen-key filter circuit assembly and method' [patent_app_type] => B1 [patent_app_number] => 09/778288 [patent_app_country] => US [patent_app_date] => 2001-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2534 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/407/06407627.pdf [firstpage_image] =>[orig_patent_app_number] => 09778288 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/778288
Tunable sallen-key filter circuit assembly and method Feb 6, 2001 Issued
Array ( [id] => 1462190 [patent_doc_number] => 06392461 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Clock modulator' [patent_app_type] => B1 [patent_app_number] => 09/774689 [patent_app_country] => US [patent_app_date] => 2001-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3793 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/392/06392461.pdf [firstpage_image] =>[orig_patent_app_number] => 09774689 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/774689
Clock modulator Jan 31, 2001 Issued
Array ( [id] => 1399469 [patent_doc_number] => 06549052 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-15 [patent_title] => 'Variable delay circuit' [patent_app_type] => B2 [patent_app_number] => 09/771577 [patent_app_country] => US [patent_app_date] => 2001-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 10544 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/549/06549052.pdf [firstpage_image] =>[orig_patent_app_number] => 09771577 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/771577
Variable delay circuit Jan 29, 2001 Issued
Array ( [id] => 6947211 [patent_doc_number] => 20010020857 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-13 [patent_title] => 'Device for the regeneration of a clock signal' [patent_app_type] => new [patent_app_number] => 09/771364 [patent_app_country] => US [patent_app_date] => 2001-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3791 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 14 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0020/20010020857.pdf [firstpage_image] =>[orig_patent_app_number] => 09771364 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/771364
Device for the regeneration of a clock signal Jan 25, 2001 Issued
Array ( [id] => 1476889 [patent_doc_number] => 06388492 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-05-14 [patent_title] => 'Clock generation circuit' [patent_app_type] => B2 [patent_app_number] => 09/769354 [patent_app_country] => US [patent_app_date] => 2001-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 46 [patent_no_of_words] => 6435 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/388/06388492.pdf [firstpage_image] =>[orig_patent_app_number] => 09769354 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/769354
Clock generation circuit Jan 25, 2001 Issued
Array ( [id] => 6222329 [patent_doc_number] => 20020003447 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-10 [patent_title] => 'Trimming circuit of semiconductor integrated device' [patent_app_type] => new [patent_app_number] => 09/769241 [patent_app_country] => US [patent_app_date] => 2001-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3872 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20020003447.pdf [firstpage_image] =>[orig_patent_app_number] => 09769241 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/769241
Trimming circuit of semiconductor integrated device Jan 25, 2001 Abandoned
Array ( [id] => 1535055 [patent_doc_number] => 06411130 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-25 [patent_title] => 'Method and system for reliably providing a lock indication' [patent_app_type] => B1 [patent_app_number] => 09/769059 [patent_app_country] => US [patent_app_date] => 2001-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1843 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/411/06411130.pdf [firstpage_image] =>[orig_patent_app_number] => 09769059 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/769059
Method and system for reliably providing a lock indication Jan 22, 2001 Issued
Array ( [id] => 1230420 [patent_doc_number] => 06696876 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-24 [patent_title] => 'Clock interpolation through capacitive weighting' [patent_app_type] => B2 [patent_app_number] => 09/759981 [patent_app_country] => US [patent_app_date] => 2001-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2963 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/696/06696876.pdf [firstpage_image] =>[orig_patent_app_number] => 09759981 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/759981
Clock interpolation through capacitive weighting Jan 11, 2001 Issued
Array ( [id] => 6417950 [patent_doc_number] => 20020125926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-12 [patent_title] => 'DELAY LOCK LOOP AND UPDATE METHOD WITH LIMITED DRIFT AND IMPROVED POWER SAVINGS' [patent_app_type] => new [patent_app_number] => 09/758479 [patent_app_country] => US [patent_app_date] => 2001-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2653 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20020125926.pdf [firstpage_image] =>[orig_patent_app_number] => 09758479 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/758479
Delay lock loop and update method with limited drift and improved power savings Jan 10, 2001 Issued
Array ( [id] => 6886013 [patent_doc_number] => 20010019282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-06 [patent_title] => 'Pulse generator' [patent_app_type] => new [patent_app_number] => 09/758998 [patent_app_country] => US [patent_app_date] => 2001-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3135 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20010019282.pdf [firstpage_image] =>[orig_patent_app_number] => 09758998 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/758998
Pulse generator for generating an output in response to a delay time Jan 10, 2001 Issued
Array ( [id] => 7051899 [patent_doc_number] => 20010001231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-05-17 [patent_title] => 'Comparator circuit' [patent_app_type] => new-utility [patent_app_number] => 09/759817 [patent_app_country] => US [patent_app_date] => 2001-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5878 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20010001231.pdf [firstpage_image] =>[orig_patent_app_number] => 09759817 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/759817
Comparator circuit Jan 9, 2001 Issued
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