Search

Linh M. Nguyen

Examiner (ID: 16124)

Most Active Art Unit
2816
Art Unit(s)
3992, 2816, 2857
Total Applications
1009
Issued Applications
920
Pending Applications
36
Abandoned Applications
53

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7118040 [patent_doc_number] => 20010001544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-05-24 [patent_title] => 'Voltage divider circuit' [patent_app_type] => new-utility [patent_app_number] => 09/760071 [patent_app_country] => US [patent_app_date] => 2001-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5883 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20010001544.pdf [firstpage_image] =>[orig_patent_app_number] => 09760071 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/760071
Voltage divider circuit Jan 9, 2001 Issued
Array ( [id] => 1436989 [patent_doc_number] => 06356127 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Phase locked loop' [patent_app_type] => B1 [patent_app_number] => 09/757554 [patent_app_country] => US [patent_app_date] => 2001-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4343 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/356/06356127.pdf [firstpage_image] =>[orig_patent_app_number] => 09757554 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/757554
Phase locked loop Jan 9, 2001 Issued
Array ( [id] => 1383111 [patent_doc_number] => 06563365 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-13 [patent_title] => 'Low-noise four-quadrant multiplier method and apparatus' [patent_app_type] => B2 [patent_app_number] => 09/758533 [patent_app_country] => US [patent_app_date] => 2001-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2701 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/563/06563365.pdf [firstpage_image] =>[orig_patent_app_number] => 09758533 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/758533
Low-noise four-quadrant multiplier method and apparatus Jan 9, 2001 Issued
Array ( [id] => 6877395 [patent_doc_number] => 20010002881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-06-07 [patent_title] => 'Oscillator circuit' [patent_app_type] => new-utility [patent_app_number] => 09/760108 [patent_app_country] => US [patent_app_date] => 2001-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5862 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20010002881.pdf [firstpage_image] =>[orig_patent_app_number] => 09760108 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/760108
Oscillator circuit Jan 9, 2001 Abandoned
Array ( [id] => 1548294 [patent_doc_number] => 06445230 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Programmable digital phase lock loop' [patent_app_type] => B1 [patent_app_number] => 09/750671 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 6572 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/445/06445230.pdf [firstpage_image] =>[orig_patent_app_number] => 09750671 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/750671
Programmable digital phase lock loop Dec 28, 2000 Issued
Array ( [id] => 1424248 [patent_doc_number] => 06518811 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-11 [patent_title] => 'Software programmable delay circuit' [patent_app_type] => B1 [patent_app_number] => 09/752367 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7624 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 313 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/518/06518811.pdf [firstpage_image] =>[orig_patent_app_number] => 09752367 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/752367
Software programmable delay circuit Dec 28, 2000 Issued
Array ( [id] => 1399333 [patent_doc_number] => 06549046 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-15 [patent_title] => 'Method and apparatus for phase aligning two clock signals utilizing a programmable phase adjustment circuit' [patent_app_type] => B1 [patent_app_number] => 09/751995 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 8107 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/549/06549046.pdf [firstpage_image] =>[orig_patent_app_number] => 09751995 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/751995
Method and apparatus for phase aligning two clock signals utilizing a programmable phase adjustment circuit Dec 28, 2000 Issued
Array ( [id] => 6578495 [patent_doc_number] => 20020084817 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-04 [patent_title] => 'DUTY CYCLE CONTROL LOOP' [patent_app_type] => new [patent_app_number] => 09/752250 [patent_app_country] => US [patent_app_date] => 2000-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2006 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20020084817.pdf [firstpage_image] =>[orig_patent_app_number] => 09752250 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/752250
Duty cycle control loop Dec 27, 2000 Issued
Array ( [id] => 6891393 [patent_doc_number] => 20010017555 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-30 [patent_title] => 'Method of dividing the frequency of a signal' [patent_app_type] => new [patent_app_number] => 09/749148 [patent_app_country] => US [patent_app_date] => 2000-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3677 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20010017555.pdf [firstpage_image] =>[orig_patent_app_number] => 09749148 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/749148
Method of dividing the frequency of a signal Dec 26, 2000 Issued
Array ( [id] => 1537068 [patent_doc_number] => 06489822 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-03 [patent_title] => 'Delay locked loop with delay control unit for noise elimination' [patent_app_type] => B2 [patent_app_number] => 09/747886 [patent_app_country] => US [patent_app_date] => 2000-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2800 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/489/06489822.pdf [firstpage_image] =>[orig_patent_app_number] => 09747886 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/747886
Delay locked loop with delay control unit for noise elimination Dec 21, 2000 Issued
Array ( [id] => 6933576 [patent_doc_number] => 20010054920 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-27 [patent_title] => 'Semiconductor device capable of internally adjusting delayed amount of a clock signal' [patent_app_type] => new [patent_app_number] => 09/741803 [patent_app_country] => US [patent_app_date] => 2000-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6218 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20010054920.pdf [firstpage_image] =>[orig_patent_app_number] => 09741803 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/741803
Semiconductor device capable of internally adjusting delayed amount of a clock signal Dec 21, 2000 Issued
Array ( [id] => 1497905 [patent_doc_number] => 06404246 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Precision clock synthesizer using RC oscillator and calibration circuit' [patent_app_type] => B1 [patent_app_number] => 09/741971 [patent_app_country] => US [patent_app_date] => 2000-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3431 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/404/06404246.pdf [firstpage_image] =>[orig_patent_app_number] => 09741971 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/741971
Precision clock synthesizer using RC oscillator and calibration circuit Dec 19, 2000 Issued
Array ( [id] => 1169499 [patent_doc_number] => 06759889 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-06 [patent_title] => 'Diode multiplexer circuit and electronic device incorporating the same' [patent_app_type] => B2 [patent_app_number] => 09/741673 [patent_app_country] => US [patent_app_date] => 2000-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5406 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/759/06759889.pdf [firstpage_image] =>[orig_patent_app_number] => 09741673 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/741673
Diode multiplexer circuit and electronic device incorporating the same Dec 18, 2000 Issued
Array ( [id] => 1464119 [patent_doc_number] => 06351156 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'Noise reduction circuit' [patent_app_type] => B1 [patent_app_number] => 09/740104 [patent_app_country] => US [patent_app_date] => 2000-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3913 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/351/06351156.pdf [firstpage_image] =>[orig_patent_app_number] => 09740104 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/740104
Noise reduction circuit Dec 17, 2000 Issued
Array ( [id] => 7040300 [patent_doc_number] => 20010005162 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-06-28 [patent_title] => 'Notch filter implemented using analog sampling ' [patent_app_type] => new-utility [patent_app_number] => 09/739729 [patent_app_country] => US [patent_app_date] => 2000-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 9595 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20010005162.pdf [firstpage_image] =>[orig_patent_app_number] => 09739729 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/739729
Notch filter implemented using analog sampling Dec 17, 2000 Issued
Array ( [id] => 1497958 [patent_doc_number] => 06404258 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-06-11 [patent_title] => 'Delay circuit having low operating environment dependency' [patent_app_type] => B2 [patent_app_number] => 09/735635 [patent_app_country] => US [patent_app_date] => 2000-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 57 [patent_no_of_words] => 28173 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/404/06404258.pdf [firstpage_image] =>[orig_patent_app_number] => 09735635 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/735635
Delay circuit having low operating environment dependency Dec 13, 2000 Issued
Array ( [id] => 1591863 [patent_doc_number] => 06483379 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-19 [patent_title] => 'Input circuit for relatively high current AC signals to be monitored' [patent_app_type] => B1 [patent_app_number] => 09/737025 [patent_app_country] => US [patent_app_date] => 2000-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2192 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/483/06483379.pdf [firstpage_image] =>[orig_patent_app_number] => 09737025 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/737025
Input circuit for relatively high current AC signals to be monitored Dec 13, 2000 Issued
Array ( [id] => 1522650 [patent_doc_number] => 06414540 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Input filter stage for a data stream, and method for filtering a data stream' [patent_app_type] => B1 [patent_app_number] => 09/737077 [patent_app_country] => US [patent_app_date] => 2000-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2810 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/414/06414540.pdf [firstpage_image] =>[orig_patent_app_number] => 09737077 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/737077
Input filter stage for a data stream, and method for filtering a data stream Dec 13, 2000 Issued
Array ( [id] => 1544940 [patent_doc_number] => 06373309 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Duty cycle compensation circuit of delay locked loop for Rambus DRAM' [patent_app_type] => B1 [patent_app_number] => 09/735642 [patent_app_country] => US [patent_app_date] => 2000-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3484 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/373/06373309.pdf [firstpage_image] =>[orig_patent_app_number] => 09735642 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/735642
Duty cycle compensation circuit of delay locked loop for Rambus DRAM Dec 13, 2000 Issued
Array ( [id] => 7630846 [patent_doc_number] => 06636086 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-10-21 [patent_title] => 'High performance microwave synthesizer using multiple-modulator fractional-N divider' [patent_app_type] => B2 [patent_app_number] => 09/733870 [patent_app_country] => US [patent_app_date] => 2000-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2389 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/636/06636086.pdf [firstpage_image] =>[orig_patent_app_number] => 09733870 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/733870
High performance microwave synthesizer using multiple-modulator fractional-N divider Dec 7, 2000 Issued
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