Search

Linh M. Nguyen

Examiner (ID: 16124)

Most Active Art Unit
2816
Art Unit(s)
3992, 2816, 2857
Total Applications
1009
Issued Applications
920
Pending Applications
36
Abandoned Applications
53

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6900939 [patent_doc_number] => 20010022522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-20 [patent_title] => 'Clock generating circuit for compensation of delay difference using closed loop analog synchronous mirror delay structure' [patent_app_type] => new [patent_app_number] => 09/730634 [patent_app_country] => US [patent_app_date] => 2000-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5395 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20010022522.pdf [firstpage_image] =>[orig_patent_app_number] => 09730634 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/730634
Clock generating circuit for compensation of delay difference using closed loop analog synchronous mirror delay structure Dec 5, 2000 Issued
Array ( [id] => 5826365 [patent_doc_number] => 20020067193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-06 [patent_title] => 'COMMON BIAS AND DIFFERENTIAL STRUCTURE BASED DLL WITH FAST LOCKUP CIRCUIT AND CURRENT RANGE CALIBRATION FOR PROCESS VARIATION' [patent_app_type] => new [patent_app_number] => 09/730890 [patent_app_country] => US [patent_app_date] => 2000-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4946 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20020067193.pdf [firstpage_image] =>[orig_patent_app_number] => 09730890 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/730890
Common bias and differential structure based DLL with fast lockup circuit and current range calibration for process variation Dec 5, 2000 Issued
Array ( [id] => 7104913 [patent_doc_number] => 20010004221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-06-21 [patent_title] => 'Variable capacitance circuit' [patent_app_type] => new-utility [patent_app_number] => 09/730448 [patent_app_country] => US [patent_app_date] => 2000-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1434 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20010004221.pdf [firstpage_image] =>[orig_patent_app_number] => 09730448 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/730448
Variable capacitance circuit Dec 4, 2000 Issued
Array ( [id] => 7635887 [patent_doc_number] => 06380773 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-30 [patent_title] => 'Prescalar using fraction division theory' [patent_app_type] => B1 [patent_app_number] => 09/727945 [patent_app_country] => US [patent_app_date] => 2000-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5217 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 9 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/380/06380773.pdf [firstpage_image] =>[orig_patent_app_number] => 09727945 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/727945
Prescalar using fraction division theory Nov 30, 2000 Issued
Array ( [id] => 6124548 [patent_doc_number] => 20020075045 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-20 [patent_title] => 'Frequency multiplier' [patent_app_type] => new [patent_app_number] => 09/726123 [patent_app_country] => US [patent_app_date] => 2000-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4631 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0075/20020075045.pdf [firstpage_image] =>[orig_patent_app_number] => 09726123 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/726123
Frequency multiplier Nov 29, 2000 Abandoned
Array ( [id] => 6597782 [patent_doc_number] => 20020063587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-30 [patent_title] => 'Apparatus and method for odd integer signal division' [patent_app_type] => new [patent_app_number] => 09/727840 [patent_app_country] => US [patent_app_date] => 2000-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2035 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20020063587.pdf [firstpage_image] =>[orig_patent_app_number] => 09727840 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/727840
Apparatus and method for odd integer signal division Nov 29, 2000 Issued
Array ( [id] => 1311964 [patent_doc_number] => 06617904 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-09 [patent_title] => 'Electronic circuit with clock generating circuit' [patent_app_type] => B1 [patent_app_number] => 09/709263 [patent_app_country] => US [patent_app_date] => 2000-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1464 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/617/06617904.pdf [firstpage_image] =>[orig_patent_app_number] => 09709263 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/709263
Electronic circuit with clock generating circuit Nov 8, 2000 Issued
Array ( [id] => 7646866 [patent_doc_number] => 06476652 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-05 [patent_title] => 'Delay locked loop for use in synchronous dynamic random access memory' [patent_app_type] => B1 [patent_app_number] => 09/703406 [patent_app_country] => US [patent_app_date] => 2000-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3554 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 17 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/476/06476652.pdf [firstpage_image] =>[orig_patent_app_number] => 09703406 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/703406
Delay locked loop for use in synchronous dynamic random access memory Oct 30, 2000 Issued
Array ( [id] => 1424267 [patent_doc_number] => 06518813 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-11 [patent_title] => 'Clock generating circuit and semiconductor integrated circuit using the same' [patent_app_type] => B1 [patent_app_number] => 09/647160 [patent_app_country] => US [patent_app_date] => 2000-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 7132 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/518/06518813.pdf [firstpage_image] =>[orig_patent_app_number] => 09647160 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/647160
Clock generating circuit and semiconductor integrated circuit using the same Oct 18, 2000 Issued
Array ( [id] => 4389102 [patent_doc_number] => 06294935 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Built-in-self-test circuitry for testing a phase locked loop circuit' [patent_app_type] => 1 [patent_app_number] => 9/690267 [patent_app_country] => US [patent_app_date] => 2000-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1773 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/294/06294935.pdf [firstpage_image] =>[orig_patent_app_number] => 690267 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/690267
Built-in-self-test circuitry for testing a phase locked loop circuit Oct 16, 2000 Issued
Array ( [id] => 4336620 [patent_doc_number] => 06320435 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'PLL circuit which can reduce phase offset without increase in operation voltage' [patent_app_type] => 1 [patent_app_number] => 9/688967 [patent_app_country] => US [patent_app_date] => 2000-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8649 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/320/06320435.pdf [firstpage_image] =>[orig_patent_app_number] => 688967 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/688967
PLL circuit which can reduce phase offset without increase in operation voltage Oct 16, 2000 Issued
Array ( [id] => 4334124 [patent_doc_number] => 06329861 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Clock generator circuit' [patent_app_type] => 1 [patent_app_number] => 9/690586 [patent_app_country] => US [patent_app_date] => 2000-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2071 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/329/06329861.pdf [firstpage_image] =>[orig_patent_app_number] => 690586 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/690586
Clock generator circuit Oct 16, 2000 Issued
Array ( [id] => 1583656 [patent_doc_number] => 06424189 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'Apparatus and system for multi-stage event synchronization' [patent_app_type] => B1 [patent_app_number] => 09/687418 [patent_app_country] => US [patent_app_date] => 2000-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 4997 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/424/06424189.pdf [firstpage_image] =>[orig_patent_app_number] => 09687418 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/687418
Apparatus and system for multi-stage event synchronization Oct 12, 2000 Issued
Array ( [id] => 1453045 [patent_doc_number] => 06456158 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Digitally programmable transconductor' [patent_app_type] => B1 [patent_app_number] => 09/689811 [patent_app_country] => US [patent_app_date] => 2000-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 6252 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/456/06456158.pdf [firstpage_image] =>[orig_patent_app_number] => 09689811 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/689811
Digitally programmable transconductor Oct 12, 2000 Issued
Array ( [id] => 4277700 [patent_doc_number] => 06307411 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Wide tracking range, auto ranging, low jitter phase lock loop for swept and fixed frequency systems' [patent_app_type] => 1 [patent_app_number] => 9/689976 [patent_app_country] => US [patent_app_date] => 2000-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5740 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/307/06307411.pdf [firstpage_image] =>[orig_patent_app_number] => 689976 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/689976
Wide tracking range, auto ranging, low jitter phase lock loop for swept and fixed frequency systems Oct 12, 2000 Issued
Array ( [id] => 1535106 [patent_doc_number] => 06411147 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-25 [patent_title] => 'System and method for grouped gating control logic' [patent_app_type] => B1 [patent_app_number] => 09/685560 [patent_app_country] => US [patent_app_date] => 2000-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3840 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/411/06411147.pdf [firstpage_image] =>[orig_patent_app_number] => 09685560 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/685560
System and method for grouped gating control logic Oct 10, 2000 Issued
Array ( [id] => 1472263 [patent_doc_number] => 06407609 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-18 [patent_title] => 'Distortion precompensator and method of compensating for distortion in a transmission medium' [patent_app_type] => B1 [patent_app_number] => 09/684260 [patent_app_country] => US [patent_app_date] => 2000-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3464 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/407/06407609.pdf [firstpage_image] =>[orig_patent_app_number] => 09684260 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/684260
Distortion precompensator and method of compensating for distortion in a transmission medium Oct 5, 2000 Issued
Array ( [id] => 1588605 [patent_doc_number] => 06359489 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Clock signal generation and buffer circuit having high noise immunity and low power consumption' [patent_app_type] => B1 [patent_app_number] => 09/679985 [patent_app_country] => US [patent_app_date] => 2000-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 1765 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/359/06359489.pdf [firstpage_image] =>[orig_patent_app_number] => 09679985 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/679985
Clock signal generation and buffer circuit having high noise immunity and low power consumption Oct 4, 2000 Issued
Array ( [id] => 1544885 [patent_doc_number] => 06373293 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Self-synchronized, multi-sample, quadrature phase detector' [patent_app_type] => B1 [patent_app_number] => 09/679197 [patent_app_country] => US [patent_app_date] => 2000-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3245 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/373/06373293.pdf [firstpage_image] =>[orig_patent_app_number] => 09679197 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/679197
Self-synchronized, multi-sample, quadrature phase detector Oct 1, 2000 Issued
Array ( [id] => 4280462 [patent_doc_number] => 06323698 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Apparatus, method and system for providing LVS enables together with LVS data' [patent_app_type] => 1 [patent_app_number] => 9/675233 [patent_app_country] => US [patent_app_date] => 2000-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 23 [patent_no_of_words] => 25579 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/323/06323698.pdf [firstpage_image] =>[orig_patent_app_number] => 675233 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/675233
Apparatus, method and system for providing LVS enables together with LVS data Sep 28, 2000 Issued
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