Search

Linh M. Nguyen

Examiner (ID: 16124)

Most Active Art Unit
2816
Art Unit(s)
3992, 2816, 2857
Total Applications
1009
Issued Applications
920
Pending Applications
36
Abandoned Applications
53

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1237629 [patent_doc_number] => 06690209 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-10 [patent_title] => 'Phase detecting with parallel discharge paths' [patent_app_type] => B1 [patent_app_number] => 09/675998 [patent_app_country] => US [patent_app_date] => 2000-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3127 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/690/06690209.pdf [firstpage_image] =>[orig_patent_app_number] => 09675998 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/675998
Phase detecting with parallel discharge paths Sep 27, 2000 Issued
Array ( [id] => 4361501 [patent_doc_number] => 06292037 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Output circuit of semiconductor integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/665964 [patent_app_country] => US [patent_app_date] => 2000-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 6720 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/292/06292037.pdf [firstpage_image] =>[orig_patent_app_number] => 665964 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/665964
Output circuit of semiconductor integrated circuit Sep 20, 2000 Issued
Array ( [id] => 1591783 [patent_doc_number] => 06483363 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-19 [patent_title] => 'Storage element with stock node capacitive load' [patent_app_type] => B1 [patent_app_number] => 09/663749 [patent_app_country] => US [patent_app_date] => 2000-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4771 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/483/06483363.pdf [firstpage_image] =>[orig_patent_app_number] => 09663749 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/663749
Storage element with stock node capacitive load Sep 14, 2000 Issued
Array ( [id] => 1429883 [patent_doc_number] => 06504412 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-07 [patent_title] => 'Storage element with switched capacitor' [patent_app_type] => B1 [patent_app_number] => 09/663750 [patent_app_country] => US [patent_app_date] => 2000-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3481 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/504/06504412.pdf [firstpage_image] =>[orig_patent_app_number] => 09663750 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/663750
Storage element with switched capacitor Sep 14, 2000 Issued
Array ( [id] => 1371136 [patent_doc_number] => 06570413 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-27 [patent_title] => 'Driver circuit for switching device' [patent_app_type] => B1 [patent_app_number] => 09/661905 [patent_app_country] => US [patent_app_date] => 2000-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7872 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/570/06570413.pdf [firstpage_image] =>[orig_patent_app_number] => 09661905 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/661905
Driver circuit for switching device Sep 13, 2000 Issued
Array ( [id] => 1464166 [patent_doc_number] => 06351175 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'Mode select circuit' [patent_app_type] => B1 [patent_app_number] => 09/662367 [patent_app_country] => US [patent_app_date] => 2000-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5242 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/351/06351175.pdf [firstpage_image] =>[orig_patent_app_number] => 09662367 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/662367
Mode select circuit Sep 12, 2000 Issued
Array ( [id] => 1591823 [patent_doc_number] => 06483372 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-19 [patent_title] => 'Low temperature coefficient voltage output circuit and method' [patent_app_type] => B1 [patent_app_number] => 09/660864 [patent_app_country] => US [patent_app_date] => 2000-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 16 [patent_no_of_words] => 3730 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/483/06483372.pdf [firstpage_image] =>[orig_patent_app_number] => 09660864 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/660864
Low temperature coefficient voltage output circuit and method Sep 12, 2000 Issued
Array ( [id] => 1566740 [patent_doc_number] => 06339348 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-15 [patent_title] => 'Programmable non-overlap time output driver' [patent_app_type] => B1 [patent_app_number] => 09/660449 [patent_app_country] => US [patent_app_date] => 2000-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2897 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/339/06339348.pdf [firstpage_image] =>[orig_patent_app_number] => 09660449 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/660449
Programmable non-overlap time output driver Sep 11, 2000 Issued
Array ( [id] => 1581052 [patent_doc_number] => 06448847 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-10 [patent_title] => 'Apparatus and method for providing differential-to-single ended conversion and impedance transformation' [patent_app_type] => B1 [patent_app_number] => 09/659873 [patent_app_country] => US [patent_app_date] => 2000-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 30 [patent_no_of_words] => 9252 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/448/06448847.pdf [firstpage_image] =>[orig_patent_app_number] => 09659873 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/659873
Apparatus and method for providing differential-to-single ended conversion and impedance transformation Sep 11, 2000 Issued
Array ( [id] => 4312362 [patent_doc_number] => 06326827 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Method and a relative digital circuit of feedback regulation of the duty cycle of a clock signal' [patent_app_type] => 1 [patent_app_number] => 9/653739 [patent_app_country] => US [patent_app_date] => 2000-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3956 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/326/06326827.pdf [firstpage_image] =>[orig_patent_app_number] => 653739 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/653739
Method and a relative digital circuit of feedback regulation of the duty cycle of a clock signal Aug 31, 2000 Issued
Array ( [id] => 364045 [patent_doc_number] => 07482861 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-01-27 [patent_title] => 'Semiconductor integrated circuit device, and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 09/648764 [patent_app_country] => US [patent_app_date] => 2000-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 28 [patent_no_of_words] => 17155 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/482/07482861.pdf [firstpage_image] =>[orig_patent_app_number] => 09648764 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/648764
Semiconductor integrated circuit device, and method of manufacturing the same Aug 27, 2000 Issued
Array ( [id] => 4320309 [patent_doc_number] => 06316974 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Method and apparatus for vertically locking input and output signals' [patent_app_type] => 1 [patent_app_number] => 9/648793 [patent_app_country] => US [patent_app_date] => 2000-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 10887 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/316/06316974.pdf [firstpage_image] =>[orig_patent_app_number] => 648793 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/648793
Method and apparatus for vertically locking input and output signals Aug 25, 2000 Issued
Array ( [id] => 1190307 [patent_doc_number] => 06734708 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-11 [patent_title] => 'Controllable current source circuit and a phase locked loop equipped with such a circuit' [patent_app_type] => B1 [patent_app_number] => 09/624438 [patent_app_country] => US [patent_app_date] => 2000-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2137 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/734/06734708.pdf [firstpage_image] =>[orig_patent_app_number] => 09624438 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/624438
Controllable current source circuit and a phase locked loop equipped with such a circuit Jul 23, 2000 Issued
Array ( [id] => 1510173 [patent_doc_number] => 06441666 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'System and method for generating clock signals' [patent_app_type] => B1 [patent_app_number] => 09/620336 [patent_app_country] => US [patent_app_date] => 2000-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 3026 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/441/06441666.pdf [firstpage_image] =>[orig_patent_app_number] => 09620336 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/620336
System and method for generating clock signals Jul 19, 2000 Issued
Array ( [id] => 1441322 [patent_doc_number] => 06496048 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-17 [patent_title] => 'System and method for accurate adjustment of discrete integrated circuit delay lines' [patent_app_type] => B1 [patent_app_number] => 09/620683 [patent_app_country] => US [patent_app_date] => 2000-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3507 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/496/06496048.pdf [firstpage_image] =>[orig_patent_app_number] => 09620683 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/620683
System and method for accurate adjustment of discrete integrated circuit delay lines Jul 19, 2000 Issued
Array ( [id] => 4320190 [patent_doc_number] => 06316966 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Apparatus and method for servo-controlled self-centering phase detector' [patent_app_type] => 1 [patent_app_number] => 9/615631 [patent_app_country] => US [patent_app_date] => 2000-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 8193 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/316/06316966.pdf [firstpage_image] =>[orig_patent_app_number] => 615631 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/615631
Apparatus and method for servo-controlled self-centering phase detector Jul 12, 2000 Issued
Array ( [id] => 4322368 [patent_doc_number] => 06242965 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Phase synchronization' [patent_app_type] => 1 [patent_app_number] => 9/612380 [patent_app_country] => US [patent_app_date] => 2000-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 6211 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/242/06242965.pdf [firstpage_image] =>[orig_patent_app_number] => 612380 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/612380
Phase synchronization Jul 6, 2000 Issued
Array ( [id] => 1569188 [patent_doc_number] => 06377100 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/605057 [patent_app_country] => US [patent_app_date] => 2000-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 13693 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/377/06377100.pdf [firstpage_image] =>[orig_patent_app_number] => 09605057 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/605057
Semiconductor device Jun 27, 2000 Issued
Array ( [id] => 1476858 [patent_doc_number] => 06388482 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'DLL lock scheme with multiple phase detection' [patent_app_type] => B1 [patent_app_number] => 09/598350 [patent_app_country] => US [patent_app_date] => 2000-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4404 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/388/06388482.pdf [firstpage_image] =>[orig_patent_app_number] => 09598350 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/598350
DLL lock scheme with multiple phase detection Jun 20, 2000 Issued
Array ( [id] => 4361536 [patent_doc_number] => 06292039 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Integrated circuit phase-locked loop charge pump' [patent_app_type] => 1 [patent_app_number] => 9/597058 [patent_app_country] => US [patent_app_date] => 2000-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2407 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/292/06292039.pdf [firstpage_image] =>[orig_patent_app_number] => 597058 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/597058
Integrated circuit phase-locked loop charge pump Jun 19, 2000 Issued
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