Search

Linh M. Nguyen

Examiner (ID: 16124)

Most Active Art Unit
2816
Art Unit(s)
3992, 2816, 2857
Total Applications
1009
Issued Applications
920
Pending Applications
36
Abandoned Applications
53

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1433615 [patent_doc_number] => 06340905 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-22 [patent_title] => 'Dynamically minimizing clock tree skew in an integrated circuit' [patent_app_type] => B1 [patent_app_number] => 09/596677 [patent_app_country] => US [patent_app_date] => 2000-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9233 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/340/06340905.pdf [firstpage_image] =>[orig_patent_app_number] => 09596677 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/596677
Dynamically minimizing clock tree skew in an integrated circuit Jun 18, 2000 Issued
Array ( [id] => 4415291 [patent_doc_number] => 06300808 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'ARRANGEMENT FOR OFFSET CURRENT COMPENSATION OF PHASE DETECTOR' [patent_app_type] => 1 [patent_app_number] => 9/592062 [patent_app_country] => US [patent_app_date] => 2000-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4809 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/300/06300808.pdf [firstpage_image] =>[orig_patent_app_number] => 592062 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/592062
ARRANGEMENT FOR OFFSET CURRENT COMPENSATION OF PHASE DETECTOR Jun 11, 2000 Issued
Array ( [id] => 1510167 [patent_doc_number] => 06441665 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => B1 [patent_app_number] => 09/592261 [patent_app_country] => US [patent_app_date] => 2000-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 13729 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/441/06441665.pdf [firstpage_image] =>[orig_patent_app_number] => 09592261 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/592261
Semiconductor integrated circuit Jun 11, 2000 Issued
Array ( [id] => 1476911 [patent_doc_number] => 06388500 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Gain controller using switched capacitors' [patent_app_type] => B1 [patent_app_number] => 09/575994 [patent_app_country] => US [patent_app_date] => 2000-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5217 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/388/06388500.pdf [firstpage_image] =>[orig_patent_app_number] => 09575994 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/575994
Gain controller using switched capacitors May 22, 2000 Issued
Array ( [id] => 1481483 [patent_doc_number] => 06452429 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'High speed input buffer circuit for low voltage interface' [patent_app_type] => B1 [patent_app_number] => 09/574306 [patent_app_country] => US [patent_app_date] => 2000-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 5626 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/452/06452429.pdf [firstpage_image] =>[orig_patent_app_number] => 09574306 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/574306
High speed input buffer circuit for low voltage interface May 18, 2000 Issued
Array ( [id] => 4390460 [patent_doc_number] => 06278319 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Input-buffering device' [patent_app_type] => 1 [patent_app_number] => 9/574374 [patent_app_country] => US [patent_app_date] => 2000-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3143 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 471 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/278/06278319.pdf [firstpage_image] =>[orig_patent_app_number] => 574374 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/574374
Input-buffering device May 18, 2000 Issued
Array ( [id] => 4368620 [patent_doc_number] => 06255863 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Circuit and method for determining level of differential signal' [patent_app_type] => 1 [patent_app_number] => 9/573827 [patent_app_country] => US [patent_app_date] => 2000-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 6926 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/255/06255863.pdf [firstpage_image] =>[orig_patent_app_number] => 573827 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/573827
Circuit and method for determining level of differential signal May 17, 2000 Issued
Array ( [id] => 1506090 [patent_doc_number] => 06466082 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Circuit technique to deal with floating body effects' [patent_app_type] => B1 [patent_app_number] => 09/573036 [patent_app_country] => US [patent_app_date] => 2000-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4798 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/466/06466082.pdf [firstpage_image] =>[orig_patent_app_number] => 09573036 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/573036
Circuit technique to deal with floating body effects May 16, 2000 Issued
Array ( [id] => 7635869 [patent_doc_number] => 06380791 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-30 [patent_title] => 'Circuit including segmented switch array for capacitive loading reduction' [patent_app_type] => B1 [patent_app_number] => 09/572022 [patent_app_country] => US [patent_app_date] => 2000-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 4385 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/380/06380791.pdf [firstpage_image] =>[orig_patent_app_number] => 09572022 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/572022
Circuit including segmented switch array for capacitive loading reduction May 15, 2000 Issued
Array ( [id] => 1555004 [patent_doc_number] => 06348834 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-19 [patent_title] => 'Linearization of FET channel impedance for small signal applications' [patent_app_type] => B1 [patent_app_number] => 09/570996 [patent_app_country] => US [patent_app_date] => 2000-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3845 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/348/06348834.pdf [firstpage_image] =>[orig_patent_app_number] => 09570996 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/570996
Linearization of FET channel impedance for small signal applications May 14, 2000 Issued
Array ( [id] => 4414588 [patent_doc_number] => 06239636 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Digital waveform generator apparatus and method therefor' [patent_app_type] => 1 [patent_app_number] => 9/569417 [patent_app_country] => US [patent_app_date] => 2000-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 8019 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/239/06239636.pdf [firstpage_image] =>[orig_patent_app_number] => 569417 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/569417
Digital waveform generator apparatus and method therefor May 11, 2000 Issued
Array ( [id] => 4334224 [patent_doc_number] => 06329868 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Circuit for compensating curvature and temperature function of a bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 9/569970 [patent_app_country] => US [patent_app_date] => 2000-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1215 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/329/06329868.pdf [firstpage_image] =>[orig_patent_app_number] => 569970 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/569970
Circuit for compensating curvature and temperature function of a bipolar transistor May 10, 2000 Issued
Array ( [id] => 1433613 [patent_doc_number] => 06340903 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-22 [patent_title] => 'Auto-zero feedback sample-hold system' [patent_app_type] => B1 [patent_app_number] => 09/567948 [patent_app_country] => US [patent_app_date] => 2000-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4911 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/340/06340903.pdf [firstpage_image] =>[orig_patent_app_number] => 09567948 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/567948
Auto-zero feedback sample-hold system May 9, 2000 Issued
Array ( [id] => 4312256 [patent_doc_number] => 06326820 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'High-frequency high-current line driver' [patent_app_type] => 1 [patent_app_number] => 9/568645 [patent_app_country] => US [patent_app_date] => 2000-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7932 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/326/06326820.pdf [firstpage_image] =>[orig_patent_app_number] => 568645 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/568645
High-frequency high-current line driver May 9, 2000 Issued
Array ( [id] => 1554990 [patent_doc_number] => 06348830 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-19 [patent_title] => 'Subharmonic double-balanced mixer' [patent_app_type] => B1 [patent_app_number] => 09/566584 [patent_app_country] => US [patent_app_date] => 2000-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 5442 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/348/06348830.pdf [firstpage_image] =>[orig_patent_app_number] => 09566584 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/566584
Subharmonic double-balanced mixer May 7, 2000 Issued
Array ( [id] => 1510140 [patent_doc_number] => 06441659 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Frequency-doubling delay locked loop' [patent_app_type] => B1 [patent_app_number] => 09/562024 [patent_app_country] => US [patent_app_date] => 2000-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4951 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/441/06441659.pdf [firstpage_image] =>[orig_patent_app_number] => 09562024 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/562024
Frequency-doubling delay locked loop Apr 30, 2000 Issued
Array ( [id] => 1576905 [patent_doc_number] => 06469558 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-22 [patent_title] => 'Electrically adjustable pulse delay circuit' [patent_app_type] => B1 [patent_app_number] => 09/558460 [patent_app_country] => US [patent_app_date] => 2000-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2996 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/469/06469558.pdf [firstpage_image] =>[orig_patent_app_number] => 09558460 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/558460
Electrically adjustable pulse delay circuit Apr 24, 2000 Issued
Array ( [id] => 1569152 [patent_doc_number] => 06377093 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Time-to-digital converter and locking circuit and method using the same' [patent_app_type] => B1 [patent_app_number] => 09/552424 [patent_app_country] => US [patent_app_date] => 2000-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 6239 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/377/06377093.pdf [firstpage_image] =>[orig_patent_app_number] => 09552424 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/552424
Time-to-digital converter and locking circuit and method using the same Apr 18, 2000 Issued
09/381547 CONTROL DEVICE FOR PRODUCING HARD TURN-ON PULSES FOR A GATE TURN-OFF THYRISTOR Feb 6, 2000 Abandoned
Array ( [id] => 4320295 [patent_doc_number] => 06316973 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Transmission timing adjusting circuit and method' [patent_app_type] => 1 [patent_app_number] => 9/491150 [patent_app_country] => US [patent_app_date] => 2000-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2395 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/316/06316973.pdf [firstpage_image] =>[orig_patent_app_number] => 491150 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/491150
Transmission timing adjusting circuit and method Jan 25, 2000 Issued
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