Search

Linh M. Nguyen

Examiner (ID: 16124)

Most Active Art Unit
2816
Art Unit(s)
3992, 2816, 2857
Total Applications
1009
Issued Applications
920
Pending Applications
36
Abandoned Applications
53

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4414635 [patent_doc_number] => 06239641 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Delay locked loop using bidirectional delay' [patent_app_type] => 1 [patent_app_number] => 9/476380 [patent_app_country] => US [patent_app_date] => 2000-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 19 [patent_no_of_words] => 3316 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/239/06239641.pdf [firstpage_image] =>[orig_patent_app_number] => 476380 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/476380
Delay locked loop using bidirectional delay Jan 2, 2000 Issued
Array ( [id] => 4416119 [patent_doc_number] => 06229359 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Low phase noise clock multiplication' [patent_app_type] => 1 [patent_app_number] => 9/476284 [patent_app_country] => US [patent_app_date] => 1999-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 21 [patent_no_of_words] => 3061 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/229/06229359.pdf [firstpage_image] =>[orig_patent_app_number] => 476284 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/476284
Low phase noise clock multiplication Dec 30, 1999 Issued
Array ( [id] => 1462213 [patent_doc_number] => 06392466 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Apparatus, method and system for a controllable pulse clock delay arrangement to control functional race margins in a logic data path' [patent_app_type] => B1 [patent_app_number] => 09/476155 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 17078 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/392/06392466.pdf [firstpage_image] =>[orig_patent_app_number] => 09476155 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/476155
Apparatus, method and system for a controllable pulse clock delay arrangement to control functional race margins in a logic data path Dec 29, 1999 Issued
Array ( [id] => 4326650 [patent_doc_number] => 06249159 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Frequency control circuit having increased control bandwidth at lower device operating speed' [patent_app_type] => 1 [patent_app_number] => 9/475010 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6548 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/249/06249159.pdf [firstpage_image] =>[orig_patent_app_number] => 475010 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/475010
Frequency control circuit having increased control bandwidth at lower device operating speed Dec 29, 1999 Issued
Array ( [id] => 1492296 [patent_doc_number] => 06417713 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'Programmable differential delay circuit with fine delay adjustment' [patent_app_type] => B1 [patent_app_number] => 09/475466 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4387 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/417/06417713.pdf [firstpage_image] =>[orig_patent_app_number] => 09475466 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/475466
Programmable differential delay circuit with fine delay adjustment Dec 29, 1999 Issued
Array ( [id] => 1495691 [patent_doc_number] => 06342797 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-29 [patent_title] => 'Delayed locked loop clock generator using delay-pulse-delay conversion' [patent_app_type] => B1 [patent_app_number] => 09/475226 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 2842 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/342/06342797.pdf [firstpage_image] =>[orig_patent_app_number] => 09475226 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/475226
Delayed locked loop clock generator using delay-pulse-delay conversion Dec 29, 1999 Issued
Array ( [id] => 4280701 [patent_doc_number] => 06323715 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Method and apparatus for selecting a clock signal without producing a glitch' [patent_app_type] => 1 [patent_app_number] => 9/475697 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4601 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/323/06323715.pdf [firstpage_image] =>[orig_patent_app_number] => 475697 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/475697
Method and apparatus for selecting a clock signal without producing a glitch Dec 29, 1999 Issued
Array ( [id] => 4412817 [patent_doc_number] => 06232811 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Circuit for controlling setup/hold time of semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/476212 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2764 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/232/06232811.pdf [firstpage_image] =>[orig_patent_app_number] => 476212 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/476212
Circuit for controlling setup/hold time of semiconductor device Dec 29, 1999 Issued
Array ( [id] => 1495692 [patent_doc_number] => 06342798 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-29 [patent_title] => 'PLL circuit used temperature compensated VCO' [patent_app_type] => B1 [patent_app_number] => 09/476231 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2401 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/342/06342798.pdf [firstpage_image] =>[orig_patent_app_number] => 09476231 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/476231
PLL circuit used temperature compensated VCO Dec 29, 1999 Issued
Array ( [id] => 1576881 [patent_doc_number] => 06469550 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-22 [patent_title] => 'Parallel phase locked loops skew measure and dynamic skew and jitter error compensation method and apparatus' [patent_app_type] => B1 [patent_app_number] => 09/476426 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 3606 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/469/06469550.pdf [firstpage_image] =>[orig_patent_app_number] => 09476426 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/476426
Parallel phase locked loops skew measure and dynamic skew and jitter error compensation method and apparatus Dec 29, 1999 Issued
Array ( [id] => 1548313 [patent_doc_number] => 06445234 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Apparatus and method for accelerating initial lock time of delayed locked loop' [patent_app_type] => B1 [patent_app_number] => 09/473685 [patent_app_country] => US [patent_app_date] => 1999-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2420 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/445/06445234.pdf [firstpage_image] =>[orig_patent_app_number] => 09473685 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/473685
Apparatus and method for accelerating initial lock time of delayed locked loop Dec 28, 1999 Issued
Array ( [id] => 4368713 [patent_doc_number] => 06255870 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Apparatus for compensating locking error in high speed memory device with delay locked loop' [patent_app_type] => 1 [patent_app_number] => 9/474093 [patent_app_country] => US [patent_app_date] => 1999-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 2760 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 306 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/255/06255870.pdf [firstpage_image] =>[orig_patent_app_number] => 474093 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/474093
Apparatus for compensating locking error in high speed memory device with delay locked loop Dec 28, 1999 Issued
Array ( [id] => 1476929 [patent_doc_number] => 06388505 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Integrated circuit generating a voltage linear ramp having a low raise' [patent_app_type] => B1 [patent_app_number] => 09/473899 [patent_app_country] => US [patent_app_date] => 1999-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3943 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/388/06388505.pdf [firstpage_image] =>[orig_patent_app_number] => 09473899 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/473899
Integrated circuit generating a voltage linear ramp having a low raise Dec 27, 1999 Issued
Array ( [id] => 4257079 [patent_doc_number] => 06222400 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Lock-in detecting circuit having variable window for checking phase locked loop and method used therein' [patent_app_type] => 1 [patent_app_number] => 9/472950 [patent_app_country] => US [patent_app_date] => 1999-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4318 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/222/06222400.pdf [firstpage_image] =>[orig_patent_app_number] => 472950 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/472950
Lock-in detecting circuit having variable window for checking phase locked loop and method used therein Dec 26, 1999 Issued
Array ( [id] => 4361590 [patent_doc_number] => 06292043 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => 1 [patent_app_number] => 9/453795 [patent_app_country] => US [patent_app_date] => 1999-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3960 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/292/06292043.pdf [firstpage_image] =>[orig_patent_app_number] => 453795 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/453795
Semiconductor integrated circuit device Dec 2, 1999 Issued
Array ( [id] => 4322285 [patent_doc_number] => 06242959 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Programmable delay circuit and method with dummy circuit compensation' [patent_app_type] => 1 [patent_app_number] => 9/453148 [patent_app_country] => US [patent_app_date] => 1999-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3419 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/242/06242959.pdf [firstpage_image] =>[orig_patent_app_number] => 453148 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/453148
Programmable delay circuit and method with dummy circuit compensation Dec 1, 1999 Issued
Array ( [id] => 4320280 [patent_doc_number] => 06316972 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Slope generator' [patent_app_type] => 1 [patent_app_number] => 9/453771 [patent_app_country] => US [patent_app_date] => 1999-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2617 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/316/06316972.pdf [firstpage_image] =>[orig_patent_app_number] => 453771 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/453771
Slope generator Dec 1, 1999 Issued
Array ( [id] => 1548336 [patent_doc_number] => 06445238 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Method and apparatus for adjusting delay in a delay locked loop for temperature variations' [patent_app_type] => B1 [patent_app_number] => 09/452234 [patent_app_country] => US [patent_app_date] => 1999-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2765 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/445/06445238.pdf [firstpage_image] =>[orig_patent_app_number] => 09452234 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/452234
Method and apparatus for adjusting delay in a delay locked loop for temperature variations Nov 30, 1999 Issued
Array ( [id] => 4320522 [patent_doc_number] => 06316987 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Low-power low-jitter variable delay timing circuit' [patent_app_type] => 1 [patent_app_number] => 9/453368 [patent_app_country] => US [patent_app_date] => 1999-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 5286 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/316/06316987.pdf [firstpage_image] =>[orig_patent_app_number] => 453368 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/453368
Low-power low-jitter variable delay timing circuit Nov 30, 1999 Issued
Array ( [id] => 4260293 [patent_doc_number] => 06208184 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Method and device for delaying selected transitions in a digital data stream' [patent_app_type] => 1 [patent_app_number] => 9/451051 [patent_app_country] => US [patent_app_date] => 1999-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4213 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/208/06208184.pdf [firstpage_image] =>[orig_patent_app_number] => 451051 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/451051
Method and device for delaying selected transitions in a digital data stream Nov 29, 1999 Issued
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