Search

Linh M. Nguyen

Examiner (ID: 16124)

Most Active Art Unit
2816
Art Unit(s)
3992, 2816, 2857
Total Applications
1009
Issued Applications
920
Pending Applications
36
Abandoned Applications
53

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4260350 [patent_doc_number] => 06208188 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Synchronizing circuit for receiving an asynchronous input signal' [patent_app_type] => 1 [patent_app_number] => 9/318872 [patent_app_country] => US [patent_app_date] => 1999-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 5224 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/208/06208188.pdf [firstpage_image] =>[orig_patent_app_number] => 318872 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/318872
Synchronizing circuit for receiving an asynchronous input signal May 25, 1999 Issued
Array ( [id] => 4257236 [patent_doc_number] => 06222411 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Integrated circuit devices having synchronized signal generators therein' [patent_app_type] => 1 [patent_app_number] => 9/318206 [patent_app_country] => US [patent_app_date] => 1999-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2196 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/222/06222411.pdf [firstpage_image] =>[orig_patent_app_number] => 318206 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/318206
Integrated circuit devices having synchronized signal generators therein May 24, 1999 Issued
Array ( [id] => 4255996 [patent_doc_number] => 06137336 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Circuit and method for generating multiphase clock' [patent_app_type] => 1 [patent_app_number] => 9/317856 [patent_app_country] => US [patent_app_date] => 1999-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7099 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/137/06137336.pdf [firstpage_image] =>[orig_patent_app_number] => 317856 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/317856
Circuit and method for generating multiphase clock May 24, 1999 Issued
Array ( [id] => 4375834 [patent_doc_number] => 06275085 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Comparator for determining process variations' [patent_app_type] => 1 [patent_app_number] => 9/317387 [patent_app_country] => US [patent_app_date] => 1999-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5774 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/275/06275085.pdf [firstpage_image] =>[orig_patent_app_number] => 317387 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/317387
Comparator for determining process variations May 23, 1999 Issued
Array ( [id] => 4363244 [patent_doc_number] => 06218877 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Semiconductor device with delay locked loop' [patent_app_type] => 1 [patent_app_number] => 9/316037 [patent_app_country] => US [patent_app_date] => 1999-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4860 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/218/06218877.pdf [firstpage_image] =>[orig_patent_app_number] => 316037 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/316037
Semiconductor device with delay locked loop May 20, 1999 Issued
Array ( [id] => 4423953 [patent_doc_number] => 06194927 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Apparatus and method for a coincident rising edge detection circuit' [patent_app_type] => 1 [patent_app_number] => 9/314556 [patent_app_country] => US [patent_app_date] => 1999-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4872 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/194/06194927.pdf [firstpage_image] =>[orig_patent_app_number] => 314556 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/314556
Apparatus and method for a coincident rising edge detection circuit May 18, 1999 Issued
Array ( [id] => 4160817 [patent_doc_number] => 06124745 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Delay and interpolation timing structures and methods' [patent_app_type] => 1 [patent_app_number] => 9/314872 [patent_app_country] => US [patent_app_date] => 1999-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3267 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/124/06124745.pdf [firstpage_image] =>[orig_patent_app_number] => 314872 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/314872
Delay and interpolation timing structures and methods May 18, 1999 Issued
Array ( [id] => 4303712 [patent_doc_number] => 06184734 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Digital phase locked loop' [patent_app_type] => 1 [patent_app_number] => 9/230530 [patent_app_country] => US [patent_app_date] => 1999-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3059 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/184/06184734.pdf [firstpage_image] =>[orig_patent_app_number] => 230530 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/230530
Digital phase locked loop May 16, 1999 Issued
Array ( [id] => 4179303 [patent_doc_number] => 06140867 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Transconductance control circuit, particularly for continuous-time circuits' [patent_app_type] => 1 [patent_app_number] => 9/312003 [patent_app_country] => US [patent_app_date] => 1999-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2462 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/140/06140867.pdf [firstpage_image] =>[orig_patent_app_number] => 312003 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/312003
Transconductance control circuit, particularly for continuous-time circuits May 13, 1999 Issued
Array ( [id] => 4241377 [patent_doc_number] => 06118306 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Changing clock frequency' [patent_app_type] => 1 [patent_app_number] => 9/302931 [patent_app_country] => US [patent_app_date] => 1999-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7096 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/118/06118306.pdf [firstpage_image] =>[orig_patent_app_number] => 302931 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/302931
Changing clock frequency Apr 29, 1999 Issued
Array ( [id] => 4304069 [patent_doc_number] => 06198327 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Pulse generator with improved high speed performance for generating a constant pulse width' [patent_app_type] => 1 [patent_app_number] => 9/267295 [patent_app_country] => US [patent_app_date] => 1999-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9945 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/198/06198327.pdf [firstpage_image] =>[orig_patent_app_number] => 267295 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/267295
Pulse generator with improved high speed performance for generating a constant pulse width Mar 14, 1999 Issued
Array ( [id] => 4257094 [patent_doc_number] => 06222401 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Phase locked loop using gear shifting algorithm' [patent_app_type] => 1 [patent_app_number] => 9/265402 [patent_app_country] => US [patent_app_date] => 1999-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1990 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/222/06222401.pdf [firstpage_image] =>[orig_patent_app_number] => 265402 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/265402
Phase locked loop using gear shifting algorithm Mar 9, 1999 Issued
Array ( [id] => 4179316 [patent_doc_number] => 06140868 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Master tuning circuit for adjusting a slave transistor to follow a master resistor' [patent_app_type] => 1 [patent_app_number] => 9/264727 [patent_app_country] => US [patent_app_date] => 1999-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3088 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/140/06140868.pdf [firstpage_image] =>[orig_patent_app_number] => 264727 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/264727
Master tuning circuit for adjusting a slave transistor to follow a master resistor Mar 8, 1999 Issued
Array ( [id] => 4415931 [patent_doc_number] => 06229344 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Phase selection circuit' [patent_app_type] => 1 [patent_app_number] => 9/265725 [patent_app_country] => US [patent_app_date] => 1999-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4227 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 16 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/229/06229344.pdf [firstpage_image] =>[orig_patent_app_number] => 265725 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/265725
Phase selection circuit Mar 8, 1999 Issued
Array ( [id] => 4097164 [patent_doc_number] => 06133771 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Device for generating pulses of high-precision programmable duration' [patent_app_type] => 1 [patent_app_number] => 9/263757 [patent_app_country] => US [patent_app_date] => 1999-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1495 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/133/06133771.pdf [firstpage_image] =>[orig_patent_app_number] => 263757 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/263757
Device for generating pulses of high-precision programmable duration Mar 4, 1999 Issued
Array ( [id] => 4257185 [patent_doc_number] => 06222407 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Dual mode programmable delay element' [patent_app_type] => 1 [patent_app_number] => 9/263035 [patent_app_country] => US [patent_app_date] => 1999-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5322 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/222/06222407.pdf [firstpage_image] =>[orig_patent_app_number] => 263035 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/263035
Dual mode programmable delay element Mar 4, 1999 Issued
Array ( [id] => 4302759 [patent_doc_number] => 06181181 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Phase shifter for a quadrature modulator and an image suppression mixer' [patent_app_type] => 1 [patent_app_number] => 9/260483 [patent_app_country] => US [patent_app_date] => 1999-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 29 [patent_no_of_words] => 11303 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/181/06181181.pdf [firstpage_image] =>[orig_patent_app_number] => 260483 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/260483
Phase shifter for a quadrature modulator and an image suppression mixer Mar 1, 1999 Issued
Array ( [id] => 4141856 [patent_doc_number] => 06121802 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Method and circuit for generating triangular waveforms opposite in phase' [patent_app_type] => 1 [patent_app_number] => 9/260878 [patent_app_country] => US [patent_app_date] => 1999-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 3999 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/121/06121802.pdf [firstpage_image] =>[orig_patent_app_number] => 260878 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/260878
Method and circuit for generating triangular waveforms opposite in phase Mar 1, 1999 Issued
Array ( [id] => 1146180 [patent_doc_number] => 06777995 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-17 [patent_title] => 'Interlaced delay-locked loops for controlling memory-circuit timing' [patent_app_type] => B1 [patent_app_number] => 09/259625 [patent_app_country] => US [patent_app_date] => 1999-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4684 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 25 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/777/06777995.pdf [firstpage_image] =>[orig_patent_app_number] => 09259625 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/259625
Interlaced delay-locked loops for controlling memory-circuit timing Feb 25, 1999 Issued
Array ( [id] => 1146180 [patent_doc_number] => 06777995 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-17 [patent_title] => 'Interlaced delay-locked loops for controlling memory-circuit timing' [patent_app_type] => B1 [patent_app_number] => 09/259625 [patent_app_country] => US [patent_app_date] => 1999-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4684 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 25 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/777/06777995.pdf [firstpage_image] =>[orig_patent_app_number] => 09259625 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/259625
Interlaced delay-locked loops for controlling memory-circuit timing Feb 25, 1999 Issued
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