Search

Linh M. Nguyen

Examiner (ID: 16124)

Most Active Art Unit
2816
Art Unit(s)
3992, 2816, 2857
Total Applications
1009
Issued Applications
920
Pending Applications
36
Abandoned Applications
53

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1146180 [patent_doc_number] => 06777995 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-17 [patent_title] => 'Interlaced delay-locked loops for controlling memory-circuit timing' [patent_app_type] => B1 [patent_app_number] => 09/259625 [patent_app_country] => US [patent_app_date] => 1999-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4684 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 25 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/777/06777995.pdf [firstpage_image] =>[orig_patent_app_number] => 09259625 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/259625
Interlaced delay-locked loops for controlling memory-circuit timing Feb 25, 1999 Issued
Array ( [id] => 1146180 [patent_doc_number] => 06777995 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-17 [patent_title] => 'Interlaced delay-locked loops for controlling memory-circuit timing' [patent_app_type] => B1 [patent_app_number] => 09/259625 [patent_app_country] => US [patent_app_date] => 1999-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4684 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 25 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/777/06777995.pdf [firstpage_image] =>[orig_patent_app_number] => 09259625 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/259625
Interlaced delay-locked loops for controlling memory-circuit timing Feb 25, 1999 Issued
Array ( [id] => 4134794 [patent_doc_number] => 06127869 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Circuit for calibrating delay lines and method' [patent_app_type] => 1 [patent_app_number] => 9/258253 [patent_app_country] => US [patent_app_date] => 1999-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 37 [patent_no_of_words] => 9769 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/127/06127869.pdf [firstpage_image] =>[orig_patent_app_number] => 258253 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/258253
Circuit for calibrating delay lines and method Feb 24, 1999 Issued
Array ( [id] => 4413488 [patent_doc_number] => 06172544 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Timing signal generation circuit for semiconductor test system' [patent_app_type] => 1 [patent_app_number] => 9/257907 [patent_app_country] => US [patent_app_date] => 1999-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 12 [patent_no_of_words] => 3584 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/172/06172544.pdf [firstpage_image] =>[orig_patent_app_number] => 257907 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/257907
Timing signal generation circuit for semiconductor test system Feb 24, 1999 Issued
Array ( [id] => 4367298 [patent_doc_number] => 06191641 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Zero power fuse circuit using subthreshold conduction' [patent_app_type] => 1 [patent_app_number] => 9/255967 [patent_app_country] => US [patent_app_date] => 1999-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4388 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/191/06191641.pdf [firstpage_image] =>[orig_patent_app_number] => 255967 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/255967
Zero power fuse circuit using subthreshold conduction Feb 22, 1999 Issued
Array ( [id] => 4141867 [patent_doc_number] => 06121803 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Pulse generator' [patent_app_type] => 1 [patent_app_number] => 9/255738 [patent_app_country] => US [patent_app_date] => 1999-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5468 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/121/06121803.pdf [firstpage_image] =>[orig_patent_app_number] => 255738 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/255738
Pulse generator Feb 22, 1999 Issued
Array ( [id] => 4376076 [patent_doc_number] => 06275101 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Phase noise reduction circuits' [patent_app_type] => 1 [patent_app_number] => 9/125077 [patent_app_country] => US [patent_app_date] => 1999-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 2699 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/275/06275101.pdf [firstpage_image] =>[orig_patent_app_number] => 125077 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/125077
Phase noise reduction circuits Feb 18, 1999 Issued
Array ( [id] => 4364412 [patent_doc_number] => 06175257 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Integrated circuit comprising a master circuit working at a first frequency to control slave circuits working at a second frequency' [patent_app_type] => 1 [patent_app_number] => 9/253270 [patent_app_country] => US [patent_app_date] => 1999-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2868 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/175/06175257.pdf [firstpage_image] =>[orig_patent_app_number] => 253270 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/253270
Integrated circuit comprising a master circuit working at a first frequency to control slave circuits working at a second frequency Feb 18, 1999 Issued
Array ( [id] => 4377615 [patent_doc_number] => 06192326 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Event recording in a service database system' [patent_app_type] => 1 [patent_app_number] => 9/250750 [patent_app_country] => US [patent_app_date] => 1999-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 22 [patent_no_of_words] => 12374 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 438 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/192/06192326.pdf [firstpage_image] =>[orig_patent_app_number] => 250750 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/250750
Event recording in a service database system Feb 15, 1999 Issued
09/218107 LOW-CURRENT CHARGE PUMP SYSTEM Dec 20, 1998 Abandoned
Array ( [id] => 4267572 [patent_doc_number] => 06204722 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Electronic circuit for generating a stable voltage signal for polarizing during a reading step UPROM memory cells operating at low feed voltage' [patent_app_type] => 1 [patent_app_number] => 9/218796 [patent_app_country] => US [patent_app_date] => 1998-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3302 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/204/06204722.pdf [firstpage_image] =>[orig_patent_app_number] => 218796 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/218796
Electronic circuit for generating a stable voltage signal for polarizing during a reading step UPROM memory cells operating at low feed voltage Dec 20, 1998 Issued
Array ( [id] => 4303567 [patent_doc_number] => 06184724 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Voltage detection circuit' [patent_app_type] => 1 [patent_app_number] => 9/212897 [patent_app_country] => US [patent_app_date] => 1998-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 10394 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/184/06184724.pdf [firstpage_image] =>[orig_patent_app_number] => 212897 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/212897
Voltage detection circuit Dec 15, 1998 Issued
Array ( [id] => 4165120 [patent_doc_number] => 06157223 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Output buffer with switching PMOS drivers' [patent_app_type] => 1 [patent_app_number] => 9/212134 [patent_app_country] => US [patent_app_date] => 1998-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3092 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/157/06157223.pdf [firstpage_image] =>[orig_patent_app_number] => 212134 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/212134
Output buffer with switching PMOS drivers Dec 14, 1998 Issued
Array ( [id] => 4225488 [patent_doc_number] => 06087883 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Multi-tanh doublets using emitter resistors' [patent_app_type] => 1 [patent_app_number] => 9/212089 [patent_app_country] => US [patent_app_date] => 1998-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3612 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/087/06087883.pdf [firstpage_image] =>[orig_patent_app_number] => 212089 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/212089
Multi-tanh doublets using emitter resistors Dec 14, 1998 Issued
Array ( [id] => 4246364 [patent_doc_number] => 06166581 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Differential integrator having offset and gain compensation, not requiring balanced inputs' [patent_app_type] => 1 [patent_app_number] => 9/210701 [patent_app_country] => US [patent_app_date] => 1998-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3661 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 476 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/166/06166581.pdf [firstpage_image] =>[orig_patent_app_number] => 210701 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/210701
Differential integrator having offset and gain compensation, not requiring balanced inputs Dec 13, 1998 Issued
Array ( [id] => 4423901 [patent_doc_number] => 06194919 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Main amplifier' [patent_app_type] => 1 [patent_app_number] => 9/210389 [patent_app_country] => US [patent_app_date] => 1998-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3153 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/194/06194919.pdf [firstpage_image] =>[orig_patent_app_number] => 210389 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/210389
Main amplifier Dec 13, 1998 Issued
Array ( [id] => 4365287 [patent_doc_number] => 06169427 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'Sample and hold circuit having single-ended input and differential output and method' [patent_app_type] => 1 [patent_app_number] => 9/208654 [patent_app_country] => US [patent_app_date] => 1998-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 4678 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/169/06169427.pdf [firstpage_image] =>[orig_patent_app_number] => 208654 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/208654
Sample and hold circuit having single-ended input and differential output and method Dec 9, 1998 Issued
Array ( [id] => 4091483 [patent_doc_number] => 06163184 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Phase locked loop (PLL) circuit' [patent_app_type] => 1 [patent_app_number] => 9/208524 [patent_app_country] => US [patent_app_date] => 1998-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6156 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/163/06163184.pdf [firstpage_image] =>[orig_patent_app_number] => 208524 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/208524
Phase locked loop (PLL) circuit Dec 8, 1998 Issued
Array ( [id] => 4363432 [patent_doc_number] => 06218889 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Semiconductor integrated circuit device, and method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/206966 [patent_app_country] => US [patent_app_date] => 1998-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 28 [patent_no_of_words] => 16110 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/218/06218889.pdf [firstpage_image] =>[orig_patent_app_number] => 206966 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/206966
Semiconductor integrated circuit device, and method of manufacturing the same Dec 7, 1998 Issued
Array ( [id] => 4412810 [patent_doc_number] => 06232810 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Flip-flop' [patent_app_type] => 1 [patent_app_number] => 9/208618 [patent_app_country] => US [patent_app_date] => 1998-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3710 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/232/06232810.pdf [firstpage_image] =>[orig_patent_app_number] => 208618 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/208618
Flip-flop Dec 7, 1998 Issued
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