Search

Linh M. Nguyen

Examiner (ID: 16124)

Most Active Art Unit
2816
Art Unit(s)
3992, 2816, 2857
Total Applications
1009
Issued Applications
920
Pending Applications
36
Abandoned Applications
53

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4364536 [patent_doc_number] => 06175266 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Operational amplifier with CMOS transistors made using 2.5 volt process transistors' [patent_app_type] => 1 [patent_app_number] => 9/207558 [patent_app_country] => US [patent_app_date] => 1998-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4133 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 383 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/175/06175266.pdf [firstpage_image] =>[orig_patent_app_number] => 207558 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/207558
Operational amplifier with CMOS transistors made using 2.5 volt process transistors Dec 7, 1998 Issued
Array ( [id] => 4139730 [patent_doc_number] => 06147529 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Voltage sensing circuit' [patent_app_type] => 1 [patent_app_number] => 9/207472 [patent_app_country] => US [patent_app_date] => 1998-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2111 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/147/06147529.pdf [firstpage_image] =>[orig_patent_app_number] => 207472 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/207472
Voltage sensing circuit Dec 7, 1998 Issued
Array ( [id] => 4197648 [patent_doc_number] => 06154089 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Fast bus driver with reduced standby power consumption' [patent_app_type] => 1 [patent_app_number] => 9/205890 [patent_app_country] => US [patent_app_date] => 1998-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2310 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/154/06154089.pdf [firstpage_image] =>[orig_patent_app_number] => 205890 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/205890
Fast bus driver with reduced standby power consumption Dec 3, 1998 Issued
Array ( [id] => 4225478 [patent_doc_number] => 06087882 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Ultra-low power magnetically coupled digital isolator using spin valve resistors' [patent_app_type] => 1 [patent_app_number] => 9/205760 [patent_app_country] => US [patent_app_date] => 1998-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 2640 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/087/06087882.pdf [firstpage_image] =>[orig_patent_app_number] => 205760 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/205760
Ultra-low power magnetically coupled digital isolator using spin valve resistors Dec 3, 1998 Issued
Array ( [id] => 4302907 [patent_doc_number] => 06181190 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Electronic circuit and manufacturing method for electronic circuit' [patent_app_type] => 1 [patent_app_number] => 9/205606 [patent_app_country] => US [patent_app_date] => 1998-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 6021 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/181/06181190.pdf [firstpage_image] =>[orig_patent_app_number] => 205606 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/205606
Electronic circuit and manufacturing method for electronic circuit Dec 3, 1998 Issued
09/204529 CHANGING CLOCK FREQUENCY Dec 2, 1998 Abandoned
Array ( [id] => 4367155 [patent_doc_number] => 06191631 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Electric circuit comprising at least one switched capacitor and method of operating said circuit' [patent_app_type] => 1 [patent_app_number] => 9/203552 [patent_app_country] => US [patent_app_date] => 1998-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2629 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/191/06191631.pdf [firstpage_image] =>[orig_patent_app_number] => 203552 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/203552
Electric circuit comprising at least one switched capacitor and method of operating said circuit Nov 30, 1998 Issued
Array ( [id] => 4165571 [patent_doc_number] => 06114899 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Variable voltage driver circuit using current detector' [patent_app_type] => 1 [patent_app_number] => 9/200450 [patent_app_country] => US [patent_app_date] => 1998-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2186 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/114/06114899.pdf [firstpage_image] =>[orig_patent_app_number] => 200450 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/200450
Variable voltage driver circuit using current detector Nov 26, 1998 Issued
Array ( [id] => 4107899 [patent_doc_number] => 06134504 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Analyte concentration information collection and communication system' [patent_app_type] => 1 [patent_app_number] => 9/190301 [patent_app_country] => US [patent_app_date] => 1998-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5212 [patent_no_of_claims] => 65 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/134/06134504.pdf [firstpage_image] =>[orig_patent_app_number] => 190301 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/190301
Analyte concentration information collection and communication system Nov 12, 1998 Issued
Array ( [id] => 4147778 [patent_doc_number] => 06060923 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'PLL device having a simple design yet achieving reliable and accurate operation' [patent_app_type] => 1 [patent_app_number] => 9/190024 [patent_app_country] => US [patent_app_date] => 1998-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 36 [patent_no_of_words] => 7341 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/060/06060923.pdf [firstpage_image] =>[orig_patent_app_number] => 190024 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/190024
PLL device having a simple design yet achieving reliable and accurate operation Nov 11, 1998 Issued
Array ( [id] => 4412850 [patent_doc_number] => 06232814 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Method and apparatus for controlling impedance on an input-output node of an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/189541 [patent_app_country] => US [patent_app_date] => 1998-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7191 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/232/06232814.pdf [firstpage_image] =>[orig_patent_app_number] => 189541 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/189541
Method and apparatus for controlling impedance on an input-output node of an integrated circuit Nov 9, 1998 Issued
Array ( [id] => 4192532 [patent_doc_number] => 06160433 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-12 [patent_title] => 'Method for generating clock and clock generating circuit' [patent_app_type] => 1 [patent_app_number] => 9/182813 [patent_app_country] => US [patent_app_date] => 1998-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4584 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/160/06160433.pdf [firstpage_image] =>[orig_patent_app_number] => 182813 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/182813
Method for generating clock and clock generating circuit Oct 29, 1998 Issued
Array ( [id] => 4414688 [patent_doc_number] => 06239646 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'High-speed, multiple-input multiplexer scheme' [patent_app_type] => 1 [patent_app_number] => 9/182556 [patent_app_country] => US [patent_app_date] => 1998-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2129 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/239/06239646.pdf [firstpage_image] =>[orig_patent_app_number] => 182556 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/182556
High-speed, multiple-input multiplexer scheme Oct 28, 1998 Issued
Array ( [id] => 4165464 [patent_doc_number] => 06114891 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Pulse generating circuit for dynamic random access memory device' [patent_app_type] => 1 [patent_app_number] => 9/178895 [patent_app_country] => US [patent_app_date] => 1998-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 18 [patent_no_of_words] => 3480 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/114/06114891.pdf [firstpage_image] =>[orig_patent_app_number] => 178895 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/178895
Pulse generating circuit for dynamic random access memory device Oct 26, 1998 Issued
Array ( [id] => 1588571 [patent_doc_number] => 06359479 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Synchronizing data transfers between two distinct clock domains' [patent_app_type] => B1 [patent_app_number] => 09/179277 [patent_app_country] => US [patent_app_date] => 1998-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4090 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/359/06359479.pdf [firstpage_image] =>[orig_patent_app_number] => 09179277 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/179277
Synchronizing data transfers between two distinct clock domains Oct 25, 1998 Issued
Array ( [id] => 4139742 [patent_doc_number] => 06147530 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'PLL circuit' [patent_app_type] => 1 [patent_app_number] => 9/172770 [patent_app_country] => US [patent_app_date] => 1998-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 9754 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/147/06147530.pdf [firstpage_image] =>[orig_patent_app_number] => 172770 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/172770
PLL circuit Oct 14, 1998 Issued
Array ( [id] => 4142064 [patent_doc_number] => 06121814 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Tri-state bus controller' [patent_app_type] => 1 [patent_app_number] => 9/169794 [patent_app_country] => US [patent_app_date] => 1998-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2559 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/121/06121814.pdf [firstpage_image] =>[orig_patent_app_number] => 169794 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/169794
Tri-state bus controller Oct 8, 1998 Issued
Array ( [id] => 4164059 [patent_doc_number] => 06107848 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Phase synchronisation' [patent_app_type] => 1 [patent_app_number] => 9/167989 [patent_app_country] => US [patent_app_date] => 1998-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 6281 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/107/06107848.pdf [firstpage_image] =>[orig_patent_app_number] => 167989 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/167989
Phase synchronisation Oct 7, 1998 Issued
Array ( [id] => 4363484 [patent_doc_number] => 06218893 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Power circuit and clock signal detection circuit' [patent_app_type] => 1 [patent_app_number] => 9/167670 [patent_app_country] => US [patent_app_date] => 1998-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5810 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/218/06218893.pdf [firstpage_image] =>[orig_patent_app_number] => 167670 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/167670
Power circuit and clock signal detection circuit Oct 6, 1998 Issued
Array ( [id] => 4424021 [patent_doc_number] => 06194937 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Synchronous delay circuit system' [patent_app_type] => 1 [patent_app_number] => 9/166583 [patent_app_country] => US [patent_app_date] => 1998-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6639 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/194/06194937.pdf [firstpage_image] =>[orig_patent_app_number] => 166583 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/166583
Synchronous delay circuit system Oct 5, 1998 Issued
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