Search

Linh V. Nguyen

Examiner (ID: 10470, Phone: (571)272-1810 , Office: P/2845 )

Most Active Art Unit
2845
Art Unit(s)
2819, 2845, 3992
Total Applications
2300
Issued Applications
2050
Pending Applications
135
Abandoned Applications
165

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20382518 [patent_doc_number] => 20250365011 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-27 [patent_title] => ARITHMETIC ENCODER FOR ARITHMETICALLY ENCODING AND ARITHMETIC DECODER FOR ARITHMETICALLY DECODING A SEQUENCE OF INFORMATION VALUES, METHODS FOR ARITHMETICALLY ENCODING AND DECODING A SEQUENCE OF INFORMATION VALUES AND COMPUTER PROGRAM FOR IMPLEMENTING THESE METHODS [patent_app_type] => utility [patent_app_number] => 19/291819 [patent_app_country] => US [patent_app_date] => 2025-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21347 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19291819 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/291819
ARITHMETIC ENCODER FOR ARITHMETICALLY ENCODING AND ARITHMETIC DECODER FOR ARITHMETICALLY DECODING A SEQUENCE OF INFORMATION VALUES, METHODS FOR ARITHMETICALLY ENCODING AND DECODING A SEQUENCE OF INFORMATION VALUES AND COMPUTER PROGRAM FOR IMPLEMENTING THESE METHODS Aug 5, 2025 Pending
Array ( [id] => 20382518 [patent_doc_number] => 20250365011 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-27 [patent_title] => ARITHMETIC ENCODER FOR ARITHMETICALLY ENCODING AND ARITHMETIC DECODER FOR ARITHMETICALLY DECODING A SEQUENCE OF INFORMATION VALUES, METHODS FOR ARITHMETICALLY ENCODING AND DECODING A SEQUENCE OF INFORMATION VALUES AND COMPUTER PROGRAM FOR IMPLEMENTING THESE METHODS [patent_app_type] => utility [patent_app_number] => 19/291819 [patent_app_country] => US [patent_app_date] => 2025-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21347 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19291819 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/291819
ARITHMETIC ENCODER FOR ARITHMETICALLY ENCODING AND ARITHMETIC DECODER FOR ARITHMETICALLY DECODING A SEQUENCE OF INFORMATION VALUES, METHODS FOR ARITHMETICALLY ENCODING AND DECODING A SEQUENCE OF INFORMATION VALUES AND COMPUTER PROGRAM FOR IMPLEMENTING THESE METHODS Aug 5, 2025 Pending
Array ( [id] => 20373770 [patent_doc_number] => 12481202 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-25 [patent_title] => Optically based analog-digital converter [patent_app_type] => utility [patent_app_number] => 18/979213 [patent_app_country] => US [patent_app_date] => 2024-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 0 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18979213 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/979213
Optically based analog-digital converter Dec 11, 2024 Issued
Array ( [id] => 20298411 [patent_doc_number] => 20250323654 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-16 [patent_title] => CALIBRATION METHOD AND CALIBRATION SYSTEM FOR SAMPLING TIME ADAPTATION IN TIME-INTERLEAVED ADC, MEDIUM, AND CALIBRATOR [patent_app_type] => utility [patent_app_number] => 18/926355 [patent_app_country] => US [patent_app_date] => 2024-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1743 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18926355 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/926355
CALIBRATION METHOD AND CALIBRATION SYSTEM FOR SAMPLING TIME ADAPTATION IN TIME-INTERLEAVED ADC, MEDIUM, AND CALIBRATOR Oct 24, 2024 Pending
Array ( [id] => 20298411 [patent_doc_number] => 20250323654 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-16 [patent_title] => CALIBRATION METHOD AND CALIBRATION SYSTEM FOR SAMPLING TIME ADAPTATION IN TIME-INTERLEAVED ADC, MEDIUM, AND CALIBRATOR [patent_app_type] => utility [patent_app_number] => 18/926355 [patent_app_country] => US [patent_app_date] => 2024-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1743 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18926355 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/926355
CALIBRATION METHOD AND CALIBRATION SYSTEM FOR SAMPLING TIME ADAPTATION IN TIME-INTERLEAVED ADC, MEDIUM, AND CALIBRATOR Oct 24, 2024 Pending
Array ( [id] => 19560765 [patent_doc_number] => 20240372557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => ANALOG-TO-DIGITAL CONVERTER (ADC) HAVING LINEARIZATION CIRCUIT WITH RECONFIGURABLE LOOKUP TABLE (LUT) MEMORY AND CALIBRATION OPTIONS [patent_app_type] => utility [patent_app_number] => 18/772635 [patent_app_country] => US [patent_app_date] => 2024-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10773 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18772635 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/772635
Analog-to-digital converter (ADC) having linearization circuit with reconfigurable lookup table (LUT) memory and calibration options Jul 14, 2024 Issued
Array ( [id] => 19560765 [patent_doc_number] => 20240372557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => ANALOG-TO-DIGITAL CONVERTER (ADC) HAVING LINEARIZATION CIRCUIT WITH RECONFIGURABLE LOOKUP TABLE (LUT) MEMORY AND CALIBRATION OPTIONS [patent_app_type] => utility [patent_app_number] => 18/772635 [patent_app_country] => US [patent_app_date] => 2024-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10773 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18772635 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/772635
Analog-to-digital converter (ADC) having linearization circuit with reconfigurable lookup table (LUT) memory and calibration options Jul 14, 2024 Issued
Array ( [id] => 19560765 [patent_doc_number] => 20240372557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => ANALOG-TO-DIGITAL CONVERTER (ADC) HAVING LINEARIZATION CIRCUIT WITH RECONFIGURABLE LOOKUP TABLE (LUT) MEMORY AND CALIBRATION OPTIONS [patent_app_type] => utility [patent_app_number] => 18/772635 [patent_app_country] => US [patent_app_date] => 2024-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10773 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18772635 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/772635
Analog-to-digital converter (ADC) having linearization circuit with reconfigurable lookup table (LUT) memory and calibration options Jul 14, 2024 Issued
Array ( [id] => 19750198 [patent_doc_number] => 20250038763 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => ANALOG-TO-DIGITAL CONVERTER CIRCUIT, DIGITAL FILTER CIRCUIT, AND CONTROL METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/760894 [patent_app_country] => US [patent_app_date] => 2024-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6717 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18760894 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/760894
ANALOG-TO-DIGITAL CONVERTER CIRCUIT, DIGITAL FILTER CIRCUIT, AND CONTROL METHOD THEREOF Jun 30, 2024 Pending
Array ( [id] => 20448980 [patent_doc_number] => 20260005706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-01 [patent_title] => SPARSITY STORAGE ARCHITECTURES FOR TRANSPOSABLE DATASETS [patent_app_type] => utility [patent_app_number] => 18/757173 [patent_app_country] => US [patent_app_date] => 2024-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4717 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18757173 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/757173
SPARSITY STORAGE ARCHITECTURES FOR TRANSPOSABLE DATASETS Jun 26, 2024 Pending
Array ( [id] => 19688852 [patent_doc_number] => 20250007397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => SWITCHED-CAPACITOR CIRCUIT AND PIPELINED ANALOG-TO-DIGITAL CONVERTOR INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/755689 [patent_app_country] => US [patent_app_date] => 2024-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6741 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18755689 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/755689
SWITCHED-CAPACITOR CIRCUIT AND PIPELINED ANALOG-TO-DIGITAL CONVERTOR INCLUDING THE SAME Jun 26, 2024 Pending
Array ( [id] => 19635381 [patent_doc_number] => 20240413830 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => SUCCESSIVE-APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER WITH COMPARATOR ERROR DETECTION [patent_app_type] => utility [patent_app_number] => 18/739623 [patent_app_country] => US [patent_app_date] => 2024-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4093 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18739623 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/739623
SUCCESSIVE-APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER WITH COMPARATOR ERROR DETECTION Jun 10, 2024 Pending
Array ( [id] => 19774048 [patent_doc_number] => 20250055474 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => SAB BASED LOOP FILTER WITH CROSS-COUPLED STRUCTURE AND ADC INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/739534 [patent_app_country] => US [patent_app_date] => 2024-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7357 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18739534 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/739534
SAB BASED LOOP FILTER WITH CROSS-COUPLED STRUCTURE AND ADC INCLUDING THE SAME Jun 10, 2024 Pending
Array ( [id] => 19774048 [patent_doc_number] => 20250055474 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => SAB BASED LOOP FILTER WITH CROSS-COUPLED STRUCTURE AND ADC INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/739534 [patent_app_country] => US [patent_app_date] => 2024-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7357 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18739534 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/739534
SAB BASED LOOP FILTER WITH CROSS-COUPLED STRUCTURE AND ADC INCLUDING THE SAME Jun 10, 2024 Pending
Array ( [id] => 19635381 [patent_doc_number] => 20240413830 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => SUCCESSIVE-APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER WITH COMPARATOR ERROR DETECTION [patent_app_type] => utility [patent_app_number] => 18/739623 [patent_app_country] => US [patent_app_date] => 2024-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4093 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18739623 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/739623
SUCCESSIVE-APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER WITH COMPARATOR ERROR DETECTION Jun 10, 2024 Pending
Array ( [id] => 19713436 [patent_doc_number] => 20250023578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => WIDEBAND SIGNAL GENERATOR [patent_app_type] => utility [patent_app_number] => 18/739160 [patent_app_country] => US [patent_app_date] => 2024-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4116 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18739160 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/739160
WIDEBAND SIGNAL GENERATOR Jun 9, 2024 Pending
Array ( [id] => 20020406 [patent_doc_number] => 20250158628 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => ANALOG-TO-DIGITAL CONVERSION DEVICE [patent_app_type] => utility [patent_app_number] => 18/736681 [patent_app_country] => US [patent_app_date] => 2024-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3970 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18736681 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/736681
ANALOG-TO-DIGITAL CONVERSION DEVICE Jun 6, 2024 Pending
Array ( [id] => 19453671 [patent_doc_number] => 20240313801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => APPARATUS AND METHOD FOR SIGMA-DELTA MODULATOR QUANTIZATION NOISE CANCELLATION [patent_app_type] => utility [patent_app_number] => 18/673969 [patent_app_country] => US [patent_app_date] => 2024-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10514 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18673969 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/673969
APPARATUS AND METHOD FOR SIGMA-DELTA MODULATOR QUANTIZATION NOISE CANCELLATION May 23, 2024 Pending
Array ( [id] => 19453671 [patent_doc_number] => 20240313801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => APPARATUS AND METHOD FOR SIGMA-DELTA MODULATOR QUANTIZATION NOISE CANCELLATION [patent_app_type] => utility [patent_app_number] => 18/673969 [patent_app_country] => US [patent_app_date] => 2024-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10514 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18673969 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/673969
APPARATUS AND METHOD FOR SIGMA-DELTA MODULATOR QUANTIZATION NOISE CANCELLATION May 23, 2024 Pending
Array ( [id] => 19453671 [patent_doc_number] => 20240313801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => APPARATUS AND METHOD FOR SIGMA-DELTA MODULATOR QUANTIZATION NOISE CANCELLATION [patent_app_type] => utility [patent_app_number] => 18/673969 [patent_app_country] => US [patent_app_date] => 2024-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10514 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18673969 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/673969
APPARATUS AND METHOD FOR SIGMA-DELTA MODULATOR QUANTIZATION NOISE CANCELLATION May 23, 2024 Pending
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