Search

Linh V. Nguyen

Examiner (ID: 15731, Phone: (571)272-1810 , Office: P/2845 )

Most Active Art Unit
2845
Art Unit(s)
2845, 2819, 3992
Total Applications
2338
Issued Applications
2073
Pending Applications
126
Abandoned Applications
168

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18432173 [patent_doc_number] => 11677409 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-13 [patent_title] => Cloud assisted calibration of analog-to-digital converters [patent_app_type] => utility [patent_app_number] => 17/368807 [patent_app_country] => US [patent_app_date] => 2021-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 14409 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17368807 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/368807
Cloud assisted calibration of analog-to-digital converters Jul 5, 2021 Issued
Array ( [id] => 19917904 [patent_doc_number] => 12293274 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-06 [patent_title] => Method and apparatus for unification based coding for neural network model compression [patent_app_type] => utility [patent_app_number] => 17/365367 [patent_app_country] => US [patent_app_date] => 2021-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4958 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17365367 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/365367
Method and apparatus for unification based coding for neural network model compression Jun 30, 2021 Issued
Array ( [id] => 18141671 [patent_doc_number] => 20230015514 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => METHOD AND SYSTEM FOR DIGITAL EQUALIZATION OF A LINEAR OR NON-LINEAR SYSTEM [patent_app_type] => utility [patent_app_number] => 17/358044 [patent_app_country] => US [patent_app_date] => 2021-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8679 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17358044 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/358044
Method and system for digital equalization of a linear or non-linear system Jun 24, 2021 Issued
Array ( [id] => 18098465 [patent_doc_number] => 20220416806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => Circuitry for digital-to-analog conversion, differential systems and digital-to-analog converter [patent_app_type] => utility [patent_app_number] => 17/358152 [patent_app_country] => US [patent_app_date] => 2021-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9340 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17358152 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/358152
Circuitry for digital-to-analog conversion, differential systems and digital-to-analog converter Jun 24, 2021 Issued
Array ( [id] => 18191289 [patent_doc_number] => 11581900 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Analog-to-digital converter error shaping circuit and successive approximation analog-to-digital converter [patent_app_type] => utility [patent_app_number] => 17/350796 [patent_app_country] => US [patent_app_date] => 2021-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4162 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 397 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17350796 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/350796
Analog-to-digital converter error shaping circuit and successive approximation analog-to-digital converter Jun 16, 2021 Issued
Array ( [id] => 18156835 [patent_doc_number] => 11569836 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-31 [patent_title] => Multi-level signal generator and memory device including the same [patent_app_type] => utility [patent_app_number] => 17/346220 [patent_app_country] => US [patent_app_date] => 2021-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 12130 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17346220 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/346220
Multi-level signal generator and memory device including the same Jun 11, 2021 Issued
Array ( [id] => 17131193 [patent_doc_number] => 20210305962 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => ANTENNA STRUCTURE AND COMMUNICATIONS TERMINAL [patent_app_type] => utility [patent_app_number] => 17/343985 [patent_app_country] => US [patent_app_date] => 2021-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4556 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17343985 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/343985
Antenna structure and communications terminal Jun 9, 2021 Issued
Array ( [id] => 18730144 [patent_doc_number] => 20230344442 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => A/D CONVERTER AND SENSOR SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/245815 [patent_app_country] => US [patent_app_date] => 2021-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11523 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18245815 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/245815
A/D converter and sensor system including the same Jun 9, 2021 Issued
Array ( [id] => 17116490 [patent_doc_number] => 20210297087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => METHOD TO COMPENSATE FOR METASTABILITY OF ASYNCHRONOUS SAR WITHIN DELTA SIGMA MODULATOR LOOP [patent_app_type] => utility [patent_app_number] => 17/339369 [patent_app_country] => US [patent_app_date] => 2021-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12366 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17339369 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/339369
Method to compensate for metastability of asynchronous SAR within delta sigma modulator loop Jun 3, 2021 Issued
Array ( [id] => 18191287 [patent_doc_number] => 11581898 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Circuit for analog/digital conversion [patent_app_type] => utility [patent_app_number] => 17/339403 [patent_app_country] => US [patent_app_date] => 2021-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 3482 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17339403 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/339403
Circuit for analog/digital conversion Jun 3, 2021 Issued
Array ( [id] => 18137745 [patent_doc_number] => 11563440 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-24 [patent_title] => Analog-to-digital converter and analog-to-digital conversion method thereof [patent_app_type] => utility [patent_app_number] => 17/337505 [patent_app_country] => US [patent_app_date] => 2021-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 31 [patent_no_of_words] => 10429 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17337505 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/337505
Analog-to-digital converter and analog-to-digital conversion method thereof Jun 2, 2021 Issued
Array ( [id] => 17263859 [patent_doc_number] => 20210376844 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => Event Driven Quasi-Level Crossing Delta Modulator Analog To Digital Converter With Adaptive Resolution [patent_app_type] => utility [patent_app_number] => 17/335930 [patent_app_country] => US [patent_app_date] => 2021-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13385 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17335930 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/335930
Event Driven Quasi-Level Crossing Delta Modulator Analog To Digital Converter With Adaptive Resolution May 31, 2021 Abandoned
Array ( [id] => 18038847 [patent_doc_number] => 20220383063 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => REPRESENTATION OF AN ORDERED GROUP OF SYMBOLS BY HYPERVECTORS [patent_app_type] => utility [patent_app_number] => 17/331763 [patent_app_country] => US [patent_app_date] => 2021-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9407 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17331763 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/331763
Representation of an ordered group of symbols by hypervectors May 26, 2021 Issued
Array ( [id] => 18263644 [patent_doc_number] => 11611355 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-21 [patent_title] => Techniques for parameter set and header design for compressed neural network representation [patent_app_type] => utility [patent_app_number] => 17/324623 [patent_app_country] => US [patent_app_date] => 2021-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 11783 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17324623 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/324623
Techniques for parameter set and header design for compressed neural network representation May 18, 2021 Issued
Array ( [id] => 17600280 [patent_doc_number] => 20220149854 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-12 [patent_title] => Interleaved Analog-to-Digital Converter (ADC) Gain Calibration [patent_app_type] => utility [patent_app_number] => 17/322876 [patent_app_country] => US [patent_app_date] => 2021-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4751 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17322876 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/322876
Interleaved analog-to-digital converter (ADC) gain calibration May 16, 2021 Issued
Array ( [id] => 19080010 [patent_doc_number] => 11949395 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-04-02 [patent_title] => Polyphase filter control scheme for fractional resampler systems [patent_app_type] => utility [patent_app_number] => 17/320539 [patent_app_country] => US [patent_app_date] => 2021-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5275 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17320539 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/320539
Polyphase filter control scheme for fractional resampler systems May 13, 2021 Issued
Array ( [id] => 17189749 [patent_doc_number] => 20210336634 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => DATA PROCESSING APPARATUSES, METHODS, COMPUTER PROGRAMS AND COMPUTER-READABLE MEDIA [patent_app_type] => utility [patent_app_number] => 17/319220 [patent_app_country] => US [patent_app_date] => 2021-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14419 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17319220 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/319220
Data processing apparatuses, methods, computer programs and computer-readable media May 12, 2021 Issued
Array ( [id] => 17056570 [patent_doc_number] => 20210266004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-26 [patent_title] => RESIDUE TRANSFER LOOP, SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER, AND GAIN CALIBRATION METHOD [patent_app_type] => utility [patent_app_number] => 17/318143 [patent_app_country] => US [patent_app_date] => 2021-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7109 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 478 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17318143 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/318143
Residue transfer loop, successive approximation register analog-to-digital converter, and gain calibration method May 11, 2021 Issued
Array ( [id] => 17971980 [patent_doc_number] => 11489535 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-11-01 [patent_title] => Analog-to-digital converter (ADC) testing [patent_app_type] => utility [patent_app_number] => 17/302729 [patent_app_country] => US [patent_app_date] => 2021-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4953 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17302729 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/302729
Analog-to-digital converter (ADC) testing May 10, 2021 Issued
Array ( [id] => 17294133 [patent_doc_number] => 20210389972 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-16 [patent_title] => CONTROLLER AREA NETWORK APPARATUS [patent_app_type] => utility [patent_app_number] => 17/302752 [patent_app_country] => US [patent_app_date] => 2021-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10693 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17302752 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/302752
Controller area network apparatus May 10, 2021 Issued
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