
Lisa A. Kilday
Examiner (ID: 8394)
| Most Active Art Unit | 2829 |
| Art Unit(s) | 2813, 2829 |
| Total Applications | 329 |
| Issued Applications | 312 |
| Pending Applications | 7 |
| Abandoned Applications | 10 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4313242
[patent_doc_number] => 06242365
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-06-05
[patent_title] => 'Method for preventing film deposited on semiconductor wafer from cracking'
[patent_app_type] => 1
[patent_app_number] => 9/325915
[patent_app_country] => US
[patent_app_date] => 1999-06-04
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/242/06242365.pdf
[firstpage_image] =>[orig_patent_app_number] => 325915
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/325915 | Method for preventing film deposited on semiconductor wafer from cracking | Jun 3, 1999 | Issued |
Array
(
[id] => 4181629
[patent_doc_number] => 06020261
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-01
[patent_title] => 'Process for forming high aspect ratio circuit features'
[patent_app_type] => 1
[patent_app_number] => 9/323256
[patent_app_country] => US
[patent_app_date] => 1999-06-01
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[pdf_file] => patents/06/020/06020261.pdf
[firstpage_image] =>[orig_patent_app_number] => 323256
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/323256 | Process for forming high aspect ratio circuit features | May 31, 1999 | Issued |
| 09/322162 | METHOD FOR THE SURFACE TREATMENT OF VACUUM MATERIALS AND SURFACE TREATED VACUUM MATERIALS | May 27, 1999 | Abandoned |
Array
(
[id] => 4183738
[patent_doc_number] => 06159848
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[patent_issue_date] => 2000-12-12
[patent_title] => 'Method of manufacturing a semiconductor device having a high melting point metal film'
[patent_app_type] => 1
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[patent_app_date] => 1999-05-21
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/316035 | Method of manufacturing a semiconductor device having a high melting point metal film | May 20, 1999 | Issued |
Array
(
[id] => 3911624
[patent_doc_number] => 06001746
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[patent_kind] => NA
[patent_issue_date] => 1999-12-14
[patent_title] => 'Method of forming an undoped silicate glass layer on a semiconductor wafer'
[patent_app_type] => 1
[patent_app_number] => 9/314928
[patent_app_country] => US
[patent_app_date] => 1999-05-20
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Array
(
[id] => 4131612
[patent_doc_number] => 06121122
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[patent_issue_date] => 2000-09-19
[patent_title] => 'Method of contacting a silicide-based schottky diode'
[patent_app_type] => 1
[patent_app_number] => 9/312945
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[patent_app_date] => 1999-05-17
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/312945 | Method of contacting a silicide-based schottky diode | May 16, 1999 | Issued |
Array
(
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[patent_doc_number] => 06043152
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[patent_issue_date] => 2000-03-28
[patent_title] => 'Method to reduce metal damage in the HDP-CVD process by using a sacrificial dielectric film'
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[patent_app_number] => 9/310776
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/310776 | Method to reduce metal damage in the HDP-CVD process by using a sacrificial dielectric film | May 13, 1999 | Issued |
Array
(
[id] => 4081452
[patent_doc_number] => 06054398
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[patent_issue_date] => 2000-04-25
[patent_title] => 'Semiconductor interconnect barrier for fluorinated dielectrics'
[patent_app_type] => 1
[patent_app_number] => 9/311735
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[patent_app_date] => 1999-05-14
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/311735 | Semiconductor interconnect barrier for fluorinated dielectrics | May 13, 1999 | Issued |
Array
(
[id] => 4178249
[patent_doc_number] => 06037255
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-14
[patent_title] => 'Method for making integrated circuit having polymer interlayer dielectric'
[patent_app_type] => 1
[patent_app_number] => 9/310656
[patent_app_country] => US
[patent_app_date] => 1999-05-12
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[firstpage_image] =>[orig_patent_app_number] => 310656
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/310656 | Method for making integrated circuit having polymer interlayer dielectric | May 11, 1999 | Issued |
Array
(
[id] => 4107782
[patent_doc_number] => 06057218
[patent_country] => US
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[patent_issue_date] => 2000-05-02
[patent_title] => 'Method for simultaneously manufacturing poly gate and polycide gate'
[patent_app_type] => 1
[patent_app_number] => 9/307404
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[patent_app_date] => 1999-05-07
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/307404 | Method for simultaneously manufacturing poly gate and polycide gate | May 6, 1999 | Issued |
Array
(
[id] => 4178294
[patent_doc_number] => 06037258
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-14
[patent_title] => 'Method of forming a smooth copper seed layer for a copper damascene structure'
[patent_app_type] => 1
[patent_app_number] => 9/307206
[patent_app_country] => US
[patent_app_date] => 1999-05-07
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/307206 | Method of forming a smooth copper seed layer for a copper damascene structure | May 6, 1999 | Issued |
Array
(
[id] => 4207237
[patent_doc_number] => 06028013
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[patent_issue_date] => 2000-02-22
[patent_title] => 'Moisture repellant integrated circuit dielectric material combination'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/306239 | Moisture repellant integrated circuit dielectric material combination | May 5, 1999 | Issued |
Array
(
[id] => 4102208
[patent_doc_number] => 06100181
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[patent_title] => 'Low dielectric constant coating of conductive material in a damascene process for semiconductors'
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Array
(
[id] => 4153694
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Array
(
[id] => 7631343
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[patent_title] => 'Methods of heat treatment and heat treatment apparatus for silicon oxide films'
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Array
(
[id] => 4406180
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Array
(
[id] => 4294530
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Array
(
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/256634 | High-pressure anneal process for integrated circuits | Feb 23, 1999 | Issued |