
Lisa A. Kilday
Examiner (ID: 6965)
| Most Active Art Unit | 2829 |
| Art Unit(s) | 2813, 2829 |
| Total Applications | 329 |
| Issued Applications | 312 |
| Pending Applications | 7 |
| Abandoned Applications | 10 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6750603
[patent_doc_number] => 20030045123
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-03-06
[patent_title] => 'Method for fabrication of a high capacitance interpoly dielectric'
[patent_app_type] => new
[patent_app_number] => 10/267354
[patent_app_country] => US
[patent_app_date] => 2002-10-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2199
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0045/20030045123.pdf
[firstpage_image] =>[orig_patent_app_number] => 10267354
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/267354 | Method for fabrication of a high capacitance interpoly dielectric | Oct 8, 2002 | Issued |
Array
(
[id] => 1299434
[patent_doc_number] => 06623996
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-09-23
[patent_title] => 'Method of measuring contact alignment in a semiconductor device including an integrated circuit'
[patent_app_type] => B2
[patent_app_number] => 10/263679
[patent_app_country] => US
[patent_app_date] => 2002-10-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 2278
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/623/06623996.pdf
[firstpage_image] =>[orig_patent_app_number] => 10263679
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/263679 | Method of measuring contact alignment in a semiconductor device including an integrated circuit | Oct 3, 2002 | Issued |
Array
(
[id] => 6739076
[patent_doc_number] => 20030156445
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-08-21
[patent_title] => 'Method for resistance switch using short electric pulses'
[patent_app_type] => new
[patent_app_number] => 10/256358
[patent_app_country] => US
[patent_app_date] => 2002-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1626
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 38
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0156/20030156445.pdf
[firstpage_image] =>[orig_patent_app_number] => 10256358
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/256358 | Method for resistance switch using short electric pulses | Sep 25, 2002 | Issued |
Array
(
[id] => 1080521
[patent_doc_number] => 06835668
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-12-28
[patent_title] => 'Copper post-etch cleaning process'
[patent_app_type] => B2
[patent_app_number] => 10/255854
[patent_app_country] => US
[patent_app_date] => 2002-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 3
[patent_no_of_words] => 3770
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/835/06835668.pdf
[firstpage_image] =>[orig_patent_app_number] => 10255854
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/255854 | Copper post-etch cleaning process | Sep 24, 2002 | Issued |
Array
(
[id] => 1272895
[patent_doc_number] => 06653719
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-11-25
[patent_title] => 'Silicone polymer insulation film on semiconductor substrate'
[patent_app_type] => B2
[patent_app_number] => 10/253665
[patent_app_country] => US
[patent_app_date] => 2002-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 7760
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/653/06653719.pdf
[firstpage_image] =>[orig_patent_app_number] => 10253665
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/253665 | Silicone polymer insulation film on semiconductor substrate | Sep 23, 2002 | Issued |
Array
(
[id] => 7269994
[patent_doc_number] => 20040058512
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-03-25
[patent_title] => 'Optimal spike anneal ambient'
[patent_app_type] => new
[patent_app_number] => 10/251440
[patent_app_country] => US
[patent_app_date] => 2002-09-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3660
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0058/20040058512.pdf
[firstpage_image] =>[orig_patent_app_number] => 10251440
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/251440 | Optimal spike anneal ambient | Sep 19, 2002 | Issued |
Array
(
[id] => 1300178
[patent_doc_number] => 06627973
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-09-30
[patent_title] => 'Void-free interlayer dielectric (ILD0) for 0.18-micron flash memory semiconductor device'
[patent_app_type] => B1
[patent_app_number] => 10/244129
[patent_app_country] => US
[patent_app_date] => 2002-09-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 1431
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 203
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/627/06627973.pdf
[firstpage_image] =>[orig_patent_app_number] => 10244129
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/244129 | Void-free interlayer dielectric (ILD0) for 0.18-micron flash memory semiconductor device | Sep 12, 2002 | Issued |
Array
(
[id] => 6783087
[patent_doc_number] => 20030064534
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-04-03
[patent_title] => 'Method for determining optical constant of antireflective layer, and method for forming resist pattern'
[patent_app_type] => new
[patent_app_number] => 10/237735
[patent_app_country] => US
[patent_app_date] => 2002-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 10925
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0064/20030064534.pdf
[firstpage_image] =>[orig_patent_app_number] => 10237735
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/237735 | Method for determining optical constant of antireflective layer, and method for forming resist pattern | Sep 9, 2002 | Issued |
Array
(
[id] => 6651224
[patent_doc_number] => 20030008459
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-01-09
[patent_title] => 'Method of manufacturing semiconductor device and flash memory'
[patent_app_type] => new
[patent_app_number] => 10/235661
[patent_app_country] => US
[patent_app_date] => 2002-09-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 7457
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0008/20030008459.pdf
[firstpage_image] =>[orig_patent_app_number] => 10235661
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/235661 | Method of manufacturing semiconductor device and flash memory | Sep 5, 2002 | Issued |
Array
(
[id] => 6750600
[patent_doc_number] => 20030045120
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-03-06
[patent_title] => 'Photoelectrochemical undercut etching of semiconductor material'
[patent_app_type] => new
[patent_app_number] => 10/234535
[patent_app_country] => US
[patent_app_date] => 2002-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 5327
[patent_no_of_claims] => 48
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 13
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0045/20030045120.pdf
[firstpage_image] =>[orig_patent_app_number] => 10234535
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/234535 | Photoelectrochemical undercut etching of semiconductor material | Sep 2, 2002 | Issued |
Array
(
[id] => 6327370
[patent_doc_number] => 20020197816
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-12-26
[patent_title] => 'Structural integrity enhancement of dielectric films'
[patent_app_type] => new
[patent_app_number] => 10/226356
[patent_app_country] => US
[patent_app_date] => 2002-08-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3158
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0197/20020197816.pdf
[firstpage_image] =>[orig_patent_app_number] => 10226356
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/226356 | Structural integrity enhancement of dielectric films | Aug 20, 2002 | Issued |
Array
(
[id] => 1080528
[patent_doc_number] => 06835671
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-12-28
[patent_title] => 'Method of making an integrated circuit using an EUV mask formed by atomic layer deposition'
[patent_app_type] => B2
[patent_app_number] => 10/222505
[patent_app_country] => US
[patent_app_date] => 2002-08-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 2174
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/835/06835671.pdf
[firstpage_image] =>[orig_patent_app_number] => 10222505
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/222505 | Method of making an integrated circuit using an EUV mask formed by atomic layer deposition | Aug 15, 2002 | Issued |
Array
(
[id] => 7446206
[patent_doc_number] => 20040009663
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-01-15
[patent_title] => 'Method for forming contact or via plug'
[patent_app_type] => new
[patent_app_number] => 10/064765
[patent_app_country] => US
[patent_app_date] => 2002-08-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3447
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0009/20040009663.pdf
[firstpage_image] =>[orig_patent_app_number] => 10064765
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/064765 | Method for forming contact or via plug | Aug 14, 2002 | Issued |
Array
(
[id] => 1021375
[patent_doc_number] => 06887724
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-05-03
[patent_title] => 'Test element group, method of manufacturing a test element group, method of testing a semiconductor device, and semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 10/218035
[patent_app_country] => US
[patent_app_date] => 2002-08-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 45
[patent_no_of_words] => 11429
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 234
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/887/06887724.pdf
[firstpage_image] =>[orig_patent_app_number] => 10218035
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/218035 | Test element group, method of manufacturing a test element group, method of testing a semiconductor device, and semiconductor device | Aug 13, 2002 | Issued |
Array
(
[id] => 7359959
[patent_doc_number] => 20040014305
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-01-22
[patent_title] => 'Two stage etching of silicon nitride to form a nitride spacer'
[patent_app_type] => new
[patent_app_number] => 10/198825
[patent_app_country] => US
[patent_app_date] => 2002-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5511
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0014/20040014305.pdf
[firstpage_image] =>[orig_patent_app_number] => 10198825
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/198825 | Two stage etching of silicon nitride to form a nitride spacer | Jul 17, 2002 | Issued |
Array
(
[id] => 1034483
[patent_doc_number] => 06875692
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-04-05
[patent_title] => 'Copper electromigration inhibition by copper alloy formation'
[patent_app_type] => utility
[patent_app_number] => 10/191825
[patent_app_country] => US
[patent_app_date] => 2002-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 4
[patent_no_of_words] => 1321
[patent_no_of_claims] => 44
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/875/06875692.pdf
[firstpage_image] =>[orig_patent_app_number] => 10191825
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/191825 | Copper electromigration inhibition by copper alloy formation | Jul 8, 2002 | Issued |
Array
(
[id] => 1092924
[patent_doc_number] => 06825120
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-11-30
[patent_title] => 'Metal surface and film protection method to prolong Q-time after metal deposition'
[patent_app_type] => B1
[patent_app_number] => 10/176855
[patent_app_country] => US
[patent_app_date] => 2002-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 4200
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/825/06825120.pdf
[firstpage_image] =>[orig_patent_app_number] => 10176855
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/176855 | Metal surface and film protection method to prolong Q-time after metal deposition | Jun 20, 2002 | Issued |
Array
(
[id] => 6469361
[patent_doc_number] => 20020151128
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-10-17
[patent_title] => 'High-pressure anneal process for integrated circuits'
[patent_app_type] => new
[patent_app_number] => 10/128757
[patent_app_country] => US
[patent_app_date] => 2002-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1810
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0151/20020151128.pdf
[firstpage_image] =>[orig_patent_app_number] => 10128757
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/128757 | High-pressure anneal process for integrated circuits | Jun 12, 2002 | Issued |
Array
(
[id] => 6678614
[patent_doc_number] => 20030228755
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-12-11
[patent_title] => 'Method for metal patterning and improved linewidth control'
[patent_app_type] => new
[patent_app_number] => 10/165845
[patent_app_country] => US
[patent_app_date] => 2002-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3940
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0228/20030228755.pdf
[firstpage_image] =>[orig_patent_app_number] => 10165845
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/165845 | Method for metal patterning and improved linewidth control | Jun 6, 2002 | Abandoned |
Array
(
[id] => 1105076
[patent_doc_number] => 06812167
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-11-02
[patent_title] => 'Method for improving adhesion between dielectric material layers'
[patent_app_type] => B2
[patent_app_number] => 10/163045
[patent_app_country] => US
[patent_app_date] => 2002-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 5
[patent_no_of_words] => 1607
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/812/06812167.pdf
[firstpage_image] =>[orig_patent_app_number] => 10163045
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/163045 | Method for improving adhesion between dielectric material layers | Jun 4, 2002 | Issued |