Search

Lisa A. Kilday

Examiner (ID: 6965)

Most Active Art Unit
2829
Art Unit(s)
2813, 2829
Total Applications
329
Issued Applications
312
Pending Applications
7
Abandoned Applications
10

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1080501 [patent_doc_number] => 06835659 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-28 [patent_title] => 'Electrical coupling stack and processes for making same' [patent_app_type] => B2 [patent_app_number] => 10/163285 [patent_app_country] => US [patent_app_date] => 2002-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 10202 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/835/06835659.pdf [firstpage_image] =>[orig_patent_app_number] => 10163285 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/163285
Electrical coupling stack and processes for making same Jun 3, 2002 Issued
Array ( [id] => 1126548 [patent_doc_number] => 06790730 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-14 [patent_title] => 'Fabrication method for mask read only memory device' [patent_app_type] => B2 [patent_app_number] => 10/156325 [patent_app_country] => US [patent_app_date] => 2002-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2022 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/790/06790730.pdf [firstpage_image] =>[orig_patent_app_number] => 10156325 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/156325
Fabrication method for mask read only memory device May 23, 2002 Issued
Array ( [id] => 6683365 [patent_doc_number] => 20030119229 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-26 [patent_title] => 'Method for fabricating a high-voltage high-power integrated circuit device' [patent_app_type] => new [patent_app_number] => 10/153975 [patent_app_country] => US [patent_app_date] => 2002-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3850 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20030119229.pdf [firstpage_image] =>[orig_patent_app_number] => 10153975 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/153975
Method for fabricating a high-voltage high-power integrated circuit device May 22, 2002 Issued
Array ( [id] => 6408905 [patent_doc_number] => 20020182819 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-05 [patent_title] => 'Method for fabricating an insulation collar in a trench capacitor' [patent_app_type] => new [patent_app_number] => 10/153045 [patent_app_country] => US [patent_app_date] => 2002-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3999 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20020182819.pdf [firstpage_image] =>[orig_patent_app_number] => 10153045 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/153045
Method for fabricating an insulation collar in a trench capacitor May 21, 2002 Issued
Array ( [id] => 6688501 [patent_doc_number] => 20030032226 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-13 [patent_title] => 'Semiconductor integrated circuit device and method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 10/147045 [patent_app_country] => US [patent_app_date] => 2002-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5049 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20030032226.pdf [firstpage_image] =>[orig_patent_app_number] => 10147045 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/147045
Semiconductor integrated circuit device and method of manufacturing the same May 16, 2002 Issued
Array ( [id] => 6435648 [patent_doc_number] => 20020127885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-12 [patent_title] => 'High-pressure anneal process for integrated circuits' [patent_app_type] => new [patent_app_number] => 10/150319 [patent_app_country] => US [patent_app_date] => 2002-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1814 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20020127885.pdf [firstpage_image] =>[orig_patent_app_number] => 10150319 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/150319
High-pressure anneal process for integrated circuits May 16, 2002 Issued
Array ( [id] => 1155766 [patent_doc_number] => 06764929 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-20 [patent_title] => 'Method and system for providing a contact hole in a semiconductor device' [patent_app_type] => B1 [patent_app_number] => 10/151625 [patent_app_country] => US [patent_app_date] => 2002-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 1226 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/764/06764929.pdf [firstpage_image] =>[orig_patent_app_number] => 10151625 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/151625
Method and system for providing a contact hole in a semiconductor device May 15, 2002 Issued
Array ( [id] => 7629803 [patent_doc_number] => 06818553 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-16 [patent_title] => 'Etching process for high-k gate dielectrics' [patent_app_type] => B1 [patent_app_number] => 10/146315 [patent_app_country] => US [patent_app_date] => 2002-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3127 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 12 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/818/06818553.pdf [firstpage_image] =>[orig_patent_app_number] => 10146315 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/146315
Etching process for high-k gate dielectrics May 14, 2002 Issued
Array ( [id] => 1216358 [patent_doc_number] => 06706566 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-16 [patent_title] => 'Methodology for electrically induced selective breakdown of nanotubes' [patent_app_type] => B2 [patent_app_number] => 10/144402 [patent_app_country] => US [patent_app_date] => 2002-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 6256 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/706/06706566.pdf [firstpage_image] =>[orig_patent_app_number] => 10144402 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/144402
Methodology for electrically induced selective breakdown of nanotubes May 12, 2002 Issued
Array ( [id] => 1062774 [patent_doc_number] => 06849518 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-01 [patent_title] => 'Dual trench isolation using single critical lithographic patterning' [patent_app_type] => utility [patent_app_number] => 10/141545 [patent_app_country] => US [patent_app_date] => 2002-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 38 [patent_no_of_words] => 5857 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/849/06849518.pdf [firstpage_image] =>[orig_patent_app_number] => 10141545 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/141545
Dual trench isolation using single critical lithographic patterning May 6, 2002 Issued
Array ( [id] => 6635730 [patent_doc_number] => 20030211647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-13 [patent_title] => 'Method for producing a long wavelength indium gallium arsenide nitride(InGaAsN) active region' [patent_app_type] => new [patent_app_number] => 10/140625 [patent_app_country] => US [patent_app_date] => 2002-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5683 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0211/20030211647.pdf [firstpage_image] =>[orig_patent_app_number] => 10140625 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/140625
Method for producing a long wavelength indium gallium arsenide nitride(InGaAsN) active region May 6, 2002 Issued
Array ( [id] => 1177457 [patent_doc_number] => 06743715 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-01 [patent_title] => 'Dry clean process to improve device gate oxide integrity (GOI) and reliability' [patent_app_type] => B1 [patent_app_number] => 10/140645 [patent_app_country] => US [patent_app_date] => 2002-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1369 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/743/06743715.pdf [firstpage_image] =>[orig_patent_app_number] => 10140645 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/140645
Dry clean process to improve device gate oxide integrity (GOI) and reliability May 6, 2002 Issued
Array ( [id] => 1021452 [patent_doc_number] => 06887749 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-03 [patent_title] => 'Multiple oxide thicknesses for merged memory and logic applications' [patent_app_type] => utility [patent_app_number] => 10/140297 [patent_app_country] => US [patent_app_date] => 2002-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 9441 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/887/06887749.pdf [firstpage_image] =>[orig_patent_app_number] => 10140297 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/140297
Multiple oxide thicknesses for merged memory and logic applications May 5, 2002 Issued
Array ( [id] => 1277881 [patent_doc_number] => 06645839 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-11 [patent_title] => 'Method for improving a doping profile for gas phase doping' [patent_app_type] => B2 [patent_app_number] => 10/139165 [patent_app_country] => US [patent_app_date] => 2002-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3264 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/645/06645839.pdf [firstpage_image] =>[orig_patent_app_number] => 10139165 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/139165
Method for improving a doping profile for gas phase doping May 5, 2002 Issued
Array ( [id] => 6434634 [patent_doc_number] => 20020127797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-12 [patent_title] => 'Multiple oxide thicknesses for merged memory and logic applications' [patent_app_type] => new [patent_app_number] => 10/140296 [patent_app_country] => US [patent_app_date] => 2002-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9533 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20020127797.pdf [firstpage_image] =>[orig_patent_app_number] => 10140296 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/140296
Multiple oxide thicknesses for merged memory and logic applications May 5, 2002 Issued
Array ( [id] => 1119840 [patent_doc_number] => 06797615 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-28 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => B1 [patent_app_number] => 10/135335 [patent_app_country] => US [patent_app_date] => 2002-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2890 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/797/06797615.pdf [firstpage_image] =>[orig_patent_app_number] => 10135335 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/135335
Method of manufacturing a semiconductor device Apr 29, 2002 Issued
Array ( [id] => 1384676 [patent_doc_number] => 06559520 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-06 [patent_title] => 'Siloxan polymer film on semiconductor substrate' [patent_app_type] => B2 [patent_app_number] => 10/133419 [patent_app_country] => US [patent_app_date] => 2002-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6394 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/559/06559520.pdf [firstpage_image] =>[orig_patent_app_number] => 10133419 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/133419
Siloxan polymer film on semiconductor substrate Apr 24, 2002 Issued
Array ( [id] => 1341695 [patent_doc_number] => 06586338 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-01 [patent_title] => 'Methods for creating elements of predetermined shape and apparatus using these elements' [patent_app_type] => B2 [patent_app_number] => 10/131541 [patent_app_country] => US [patent_app_date] => 2002-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 38 [patent_no_of_words] => 7050 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/586/06586338.pdf [firstpage_image] =>[orig_patent_app_number] => 10131541 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/131541
Methods for creating elements of predetermined shape and apparatus using these elements Apr 22, 2002 Issued
Array ( [id] => 6863712 [patent_doc_number] => 20030189238 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-09 [patent_title] => 'Semiconductor device and method of providing regions of low substrate capacitance' [patent_app_type] => new [patent_app_number] => 10/102505 [patent_app_country] => US [patent_app_date] => 2002-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2155 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20030189238.pdf [firstpage_image] =>[orig_patent_app_number] => 10102505 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/102505
Semiconductor device and method of providing regions of low substrate capacitance Mar 19, 2002 Issued
Array ( [id] => 1256191 [patent_doc_number] => 06667249 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-23 [patent_title] => 'Minimizing coating defects in low dielectric constant films' [patent_app_type] => B1 [patent_app_number] => 10/101655 [patent_app_country] => US [patent_app_date] => 2002-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1286 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/667/06667249.pdf [firstpage_image] =>[orig_patent_app_number] => 10101655 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/101655
Minimizing coating defects in low dielectric constant films Mar 19, 2002 Issued
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