Search

Lisa A. Kilday

Examiner (ID: 6965)

Most Active Art Unit
2829
Art Unit(s)
2813, 2829
Total Applications
329
Issued Applications
312
Pending Applications
7
Abandoned Applications
10

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5917891 [patent_doc_number] => 20020113233 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-22 [patent_title] => 'Integrated circuit having photodiode device and associated fabrication process' [patent_app_type] => new [patent_app_number] => 10/044286 [patent_app_country] => US [patent_app_date] => 2002-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3294 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20020113233.pdf [firstpage_image] =>[orig_patent_app_number] => 10044286 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/044286
Integrated circuit having photodiode device and associated fabrication process Jan 10, 2002 Issued
Array ( [id] => 1245745 [patent_doc_number] => 06677233 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-13 [patent_title] => 'Material deposition from a liquefied gas solution' [patent_app_type] => B2 [patent_app_number] => 10/039095 [patent_app_country] => US [patent_app_date] => 2002-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4666 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/677/06677233.pdf [firstpage_image] =>[orig_patent_app_number] => 10039095 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/039095
Material deposition from a liquefied gas solution Jan 1, 2002 Issued
Array ( [id] => 1331901 [patent_doc_number] => 06596547 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-22 [patent_title] => 'Methods of preventing reduction of IrOx during PZT formation by metalorganic chemical vapor deposition or other processing' [patent_app_type] => B2 [patent_app_number] => 10/036805 [patent_app_country] => US [patent_app_date] => 2001-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 42 [patent_no_of_words] => 18068 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/596/06596547.pdf [firstpage_image] =>[orig_patent_app_number] => 10036805 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/036805
Methods of preventing reduction of IrOx during PZT formation by metalorganic chemical vapor deposition or other processing Dec 20, 2001 Issued
Array ( [id] => 1220080 [patent_doc_number] => 06703170 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-09 [patent_title] => 'Method and apparatus for reducing loading effects on a semiconductor manufacturing component during an etch process' [patent_app_type] => B1 [patent_app_number] => 10/023055 [patent_app_country] => US [patent_app_date] => 2001-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 6784 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/703/06703170.pdf [firstpage_image] =>[orig_patent_app_number] => 10023055 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/023055
Method and apparatus for reducing loading effects on a semiconductor manufacturing component during an etch process Dec 12, 2001 Issued
Array ( [id] => 1372331 [patent_doc_number] => 06562735 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-13 [patent_title] => 'Control of reaction rate in formation of low k carbon-containing silicon oxide dielectric material using organosilane, unsubstituted silane, and hydrogen peroxide reactants' [patent_app_type] => B1 [patent_app_number] => 10/015255 [patent_app_country] => US [patent_app_date] => 2001-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3879 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/562/06562735.pdf [firstpage_image] =>[orig_patent_app_number] => 10015255 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/015255
Control of reaction rate in formation of low k carbon-containing silicon oxide dielectric material using organosilane, unsubstituted silane, and hydrogen peroxide reactants Dec 10, 2001 Issued
Array ( [id] => 1368042 [patent_doc_number] => 06566274 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-20 [patent_title] => 'Lithography process for transparent substrates' [patent_app_type] => B1 [patent_app_number] => 09/996545 [patent_app_country] => US [patent_app_date] => 2001-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3208 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/566/06566274.pdf [firstpage_image] =>[orig_patent_app_number] => 09996545 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/996545
Lithography process for transparent substrates Nov 27, 2001 Issued
Array ( [id] => 6130250 [patent_doc_number] => 20020076947 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-20 [patent_title] => 'Combined gate cap or digit line and spacer deposition using HDP' [patent_app_type] => new [patent_app_number] => 09/989036 [patent_app_country] => US [patent_app_date] => 2001-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4127 [patent_no_of_claims] => 108 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20020076947.pdf [firstpage_image] =>[orig_patent_app_number] => 09989036 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/989036
Combined gate cap or digit line and spacer deposition using HDP Nov 20, 2001 Issued
Array ( [id] => 1274159 [patent_doc_number] => 06649537 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-18 [patent_title] => 'Intermittent pulsed oxidation process' [patent_app_type] => B1 [patent_app_number] => 10/044215 [patent_app_country] => US [patent_app_date] => 2001-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3837 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/649/06649537.pdf [firstpage_image] =>[orig_patent_app_number] => 10044215 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/044215
Intermittent pulsed oxidation process Nov 18, 2001 Issued
Array ( [id] => 1065542 [patent_doc_number] => 06846699 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-25 [patent_title] => 'Semiconductor device and method of manufacture thereof, circuit board, and electronic instrument' [patent_app_type] => utility [patent_app_number] => 09/987409 [patent_app_country] => US [patent_app_date] => 2001-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 5659 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/846/06846699.pdf [firstpage_image] =>[orig_patent_app_number] => 09987409 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/987409
Semiconductor device and method of manufacture thereof, circuit board, and electronic instrument Nov 13, 2001 Issued
Array ( [id] => 1397555 [patent_doc_number] => 06531411 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-11 [patent_title] => 'Surface roughness improvement of SIMOX substrates by controlling orientation of angle of starting material' [patent_app_type] => B1 [patent_app_number] => 10/007845 [patent_app_country] => US [patent_app_date] => 2001-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3093 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/531/06531411.pdf [firstpage_image] =>[orig_patent_app_number] => 10007845 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/007845
Surface roughness improvement of SIMOX substrates by controlling orientation of angle of starting material Nov 4, 2001 Issued
Array ( [id] => 6111521 [patent_doc_number] => 20020173168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-21 [patent_title] => 'Process for producing dielectric thin films' [patent_app_type] => new [patent_app_number] => 10/145935 [patent_app_country] => US [patent_app_date] => 2001-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 7995 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20020173168.pdf [firstpage_image] =>[orig_patent_app_number] => 10145935 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/145935
Process for producing dielectric thin films Oct 25, 2001 Issued
Array ( [id] => 1355064 [patent_doc_number] => 06576563 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-10 [patent_title] => 'Method of manufacturing a semiconductor device employing a fluorine-based etch substantially free of hydrogen' [patent_app_type] => B2 [patent_app_number] => 10/047516 [patent_app_country] => US [patent_app_date] => 2001-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3303 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/576/06576563.pdf [firstpage_image] =>[orig_patent_app_number] => 10047516 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/047516
Method of manufacturing a semiconductor device employing a fluorine-based etch substantially free of hydrogen Oct 25, 2001 Issued
Array ( [id] => 1340224 [patent_doc_number] => 06589882 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-08 [patent_title] => 'Copper post-etch cleaning process' [patent_app_type] => B2 [patent_app_number] => 10/083035 [patent_app_country] => US [patent_app_date] => 2001-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 3728 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/589/06589882.pdf [firstpage_image] =>[orig_patent_app_number] => 10083035 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/083035
Copper post-etch cleaning process Oct 23, 2001 Issued
Array ( [id] => 6657325 [patent_doc_number] => 20030077914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-24 [patent_title] => 'Method and apparatus for forming an anti-reflective coating on a substrate' [patent_app_type] => new [patent_app_number] => 10/083725 [patent_app_country] => US [patent_app_date] => 2001-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7350 [patent_no_of_claims] => 72 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20030077914.pdf [firstpage_image] =>[orig_patent_app_number] => 10083725 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/083725
Method and apparatus for forming an anti-reflective coating on a substrate Oct 23, 2001 Issued
Array ( [id] => 1089122 [patent_doc_number] => 06828201 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-12-07 [patent_title] => 'Method of manufacturing a top insulating layer for a sonos-type device' [patent_app_type] => B1 [patent_app_number] => 10/054515 [patent_app_country] => US [patent_app_date] => 2001-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 23 [patent_no_of_words] => 4309 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/828/06828201.pdf [firstpage_image] =>[orig_patent_app_number] => 10054515 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/054515
Method of manufacturing a top insulating layer for a sonos-type device Oct 21, 2001 Issued
Array ( [id] => 6874523 [patent_doc_number] => 20030194820 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-16 [patent_title] => 'Balancing planarization of layers and the effect of underlying structure on the metrology signal' [patent_app_type] => new [patent_app_number] => 10/035925 [patent_app_country] => US [patent_app_date] => 2001-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5517 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20030194820.pdf [firstpage_image] =>[orig_patent_app_number] => 10035925 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/035925
Balancing planarization of layers and the effect of underlying structure on the metrology signal Oct 21, 2001 Issued
Array ( [id] => 6081284 [patent_doc_number] => 20020081863 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-27 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => new [patent_app_number] => 09/982003 [patent_app_country] => US [patent_app_date] => 2001-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 17470 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20020081863.pdf [firstpage_image] =>[orig_patent_app_number] => 09982003 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/982003
Method of manufacturing semiconductor device Oct 18, 2001 Issued
Array ( [id] => 6870227 [patent_doc_number] => 20030082916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-01 [patent_title] => 'Method for reducing dimensions between patterns on a photoresist' [patent_app_type] => new [patent_app_number] => 09/978546 [patent_app_country] => US [patent_app_date] => 2001-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2017 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20030082916.pdf [firstpage_image] =>[orig_patent_app_number] => 09978546 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/978546
Method for reducing dimensions between patterns on a photoresist Oct 17, 2001 Issued
Array ( [id] => 6081280 [patent_doc_number] => 20020081862 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-27 [patent_title] => 'Ultra-thin SiO2 using N2O as the oxidant' [patent_app_type] => new [patent_app_number] => 09/971385 [patent_app_country] => US [patent_app_date] => 2001-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1793 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20020081862.pdf [firstpage_image] =>[orig_patent_app_number] => 09971385 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/971385
Ultra-thin SiO2using N2O as the oxidant Oct 3, 2001 Issued
Array ( [id] => 1379191 [patent_doc_number] => 06555451 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-29 [patent_title] => 'Method for making shallow diffusion junctions in semiconductors using elemental doping' [patent_app_type] => B1 [patent_app_number] => 09/964545 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4472 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/555/06555451.pdf [firstpage_image] =>[orig_patent_app_number] => 09964545 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/964545
Method for making shallow diffusion junctions in semiconductors using elemental doping Sep 27, 2001 Issued
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