
Lisa A. Kilday
Examiner (ID: 6965)
| Most Active Art Unit | 2829 |
| Art Unit(s) | 2813, 2829 |
| Total Applications | 329 |
| Issued Applications | 312 |
| Pending Applications | 7 |
| Abandoned Applications | 10 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6674368
[patent_doc_number] => 20030059971
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-03-27
[patent_title] => 'Forming indium nitride (InN) and indium gallium nitride (InGaN) quantum dots grown by metal-organic-vapor-phase-epitaxy (MOCVD)'
[patent_app_type] => new
[patent_app_number] => 09/963616
[patent_app_country] => US
[patent_app_date] => 2001-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2696
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 33
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0059/20030059971.pdf
[firstpage_image] =>[orig_patent_app_number] => 09963616
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/963616 | Forming indium nitride (InN) and indium gallium nitride (InGaN) quantum dots grown by metal-organic-vapor-phase-epitaxy (MOCVD) | Sep 26, 2001 | Issued |
Array
(
[id] => 1415729
[patent_doc_number] => 06518124
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-02-11
[patent_title] => 'Method of fabricating semiconductor device'
[patent_app_type] => B1
[patent_app_number] => 09/953855
[patent_app_country] => US
[patent_app_date] => 2001-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 15
[patent_no_of_words] => 5487
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 367
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/518/06518124.pdf
[firstpage_image] =>[orig_patent_app_number] => 09953855
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/953855 | Method of fabricating semiconductor device | Sep 17, 2001 | Issued |
Array
(
[id] => 1414623
[patent_doc_number] => 06521520
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-02-18
[patent_title] => 'Semiconductor wafer arrangement and method of processing a semiconductor wafer'
[patent_app_type] => B1
[patent_app_number] => 09/943403
[patent_app_country] => US
[patent_app_date] => 2001-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 3454
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 245
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/521/06521520.pdf
[firstpage_image] =>[orig_patent_app_number] => 09943403
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/943403 | Semiconductor wafer arrangement and method of processing a semiconductor wafer | Aug 29, 2001 | Issued |
Array
(
[id] => 5801714
[patent_doc_number] => 20020009898
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-01-24
[patent_title] => 'Method for fabricating semiconductor integrated circuit device'
[patent_app_type] => new
[patent_app_number] => 09/939600
[patent_app_country] => US
[patent_app_date] => 2001-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 18709
[patent_no_of_claims] => 55
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0009/20020009898.pdf
[firstpage_image] =>[orig_patent_app_number] => 09939600
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/939600 | Method for fabricating semiconductor integrated circuit device | Aug 27, 2001 | Issued |
Array
(
[id] => 6224763
[patent_doc_number] => 20020004315
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-01-10
[patent_title] => 'Method for fabricating semiconductor integrated circuit device'
[patent_app_type] => new
[patent_app_number] => 09/939621
[patent_app_country] => US
[patent_app_date] => 2001-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 18715
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0004/20020004315.pdf
[firstpage_image] =>[orig_patent_app_number] => 09939621
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/939621 | Method for fabricating semiconductor integrated circuit device | Aug 27, 2001 | Issued |
Array
(
[id] => 6141908
[patent_doc_number] => 20020001970
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-01-03
[patent_title] => 'Semiconductor structure useful in a self-aligned contact etch and method for making same'
[patent_app_type] => new
[patent_app_number] => 09/939905
[patent_app_country] => US
[patent_app_date] => 2001-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5473
[patent_no_of_claims] => 79
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0001/20020001970.pdf
[firstpage_image] =>[orig_patent_app_number] => 09939905
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/939905 | Semiconductor structure useful in a self-aligned contact etch and method for making same | Aug 26, 2001 | Issued |
Array
(
[id] => 1390292
[patent_doc_number] => 06544863
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-04-08
[patent_title] => 'Method of fabricating semiconductor wafers having multiple height subsurface layers'
[patent_app_type] => B1
[patent_app_number] => 09/934783
[patent_app_country] => US
[patent_app_date] => 2001-08-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 13
[patent_no_of_words] => 2336
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/544/06544863.pdf
[firstpage_image] =>[orig_patent_app_number] => 09934783
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/934783 | Method of fabricating semiconductor wafers having multiple height subsurface layers | Aug 20, 2001 | Issued |
Array
(
[id] => 6838950
[patent_doc_number] => 20030036290
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-02-20
[patent_title] => 'Method for improving the coating capability of low-k dielectric layer'
[patent_app_type] => new
[patent_app_number] => 09/931016
[patent_app_country] => US
[patent_app_date] => 2001-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1817
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0036/20030036290.pdf
[firstpage_image] =>[orig_patent_app_number] => 09931016
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/931016 | Method for improving the coating capability of low-k dielectric layer | Aug 16, 2001 | Issued |
Array
(
[id] => 5801692
[patent_doc_number] => 20020009885
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-01-24
[patent_title] => 'Method of growing surface aluminum nitride on aluminum films with low energy barrier'
[patent_app_type] => new
[patent_app_number] => 09/921225
[patent_app_country] => US
[patent_app_date] => 2001-08-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1919
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 31
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0009/20020009885.pdf
[firstpage_image] =>[orig_patent_app_number] => 09921225
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/921225 | Method of growing surface aluminum nitride on aluminum films with low energy barrier | Aug 1, 2001 | Issued |
Array
(
[id] => 1449938
[patent_doc_number] => 06455365
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-09-24
[patent_title] => 'Structural integrity enhancement of dielectric films'
[patent_app_type] => B2
[patent_app_number] => 09/912153
[patent_app_country] => US
[patent_app_date] => 2001-07-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 3150
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/455/06455365.pdf
[firstpage_image] =>[orig_patent_app_number] => 09912153
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/912153 | Structural integrity enhancement of dielectric films | Jul 22, 2001 | Issued |
Array
(
[id] => 1119908
[patent_doc_number] => 06797644
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-09-28
[patent_title] => 'Method to reduce charge interface traps and channel hot carrier degradation'
[patent_app_type] => B2
[patent_app_number] => 09/906515
[patent_app_country] => US
[patent_app_date] => 2001-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 0
[patent_no_of_words] => 1638
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/797/06797644.pdf
[firstpage_image] =>[orig_patent_app_number] => 09906515
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/906515 | Method to reduce charge interface traps and channel hot carrier degradation | Jul 15, 2001 | Issued |
Array
(
[id] => 1266541
[patent_doc_number] => 06661080
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-12-09
[patent_title] => 'Structure for backside saw cavity protection'
[patent_app_type] => B1
[patent_app_number] => 09/895996
[patent_app_country] => US
[patent_app_date] => 2001-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 4158
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 300
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/661/06661080.pdf
[firstpage_image] =>[orig_patent_app_number] => 09895996
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/895996 | Structure for backside saw cavity protection | Jun 27, 2001 | Issued |
Array
(
[id] => 1409322
[patent_doc_number] => 06528372
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-03-04
[patent_title] => 'Sidewall spacer definition of gates'
[patent_app_type] => B2
[patent_app_number] => 09/891306
[patent_app_country] => US
[patent_app_date] => 2001-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 33
[patent_no_of_words] => 5030
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/528/06528372.pdf
[firstpage_image] =>[orig_patent_app_number] => 09891306
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/891306 | Sidewall spacer definition of gates | Jun 26, 2001 | Issued |
Array
(
[id] => 1312460
[patent_doc_number] => 06610614
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-08-26
[patent_title] => 'Method for uniform nitridization of ultra-thin silicon dioxide layers in transistor gates'
[patent_app_type] => B2
[patent_app_number] => 09/885695
[patent_app_country] => US
[patent_app_date] => 2001-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 22
[patent_no_of_words] => 3943
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/610/06610614.pdf
[firstpage_image] =>[orig_patent_app_number] => 09885695
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/885695 | Method for uniform nitridization of ultra-thin silicon dioxide layers in transistor gates | Jun 19, 2001 | Issued |
Array
(
[id] => 6755991
[patent_doc_number] => 20030003768
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-01-02
[patent_title] => 'CVD PLASMA ASSISTED LOWER DIELECTRIC CONSTANT SICOH FILM'
[patent_app_type] => new
[patent_app_number] => 09/885985
[patent_app_country] => US
[patent_app_date] => 2001-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 7421
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0003/20030003768.pdf
[firstpage_image] =>[orig_patent_app_number] => 09885985
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/885985 | CVD plasma assisted lower dielectric constant sicoh film | Jun 17, 2001 | Issued |
Array
(
[id] => 1418703
[patent_doc_number] => 06514874
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-02-04
[patent_title] => 'Method of using controlled resist footing on silicon nitride substrate for smaller spacing of integrated circuit device features'
[patent_app_type] => B1
[patent_app_number] => 09/875635
[patent_app_country] => US
[patent_app_date] => 2001-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 2233
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/514/06514874.pdf
[firstpage_image] =>[orig_patent_app_number] => 09875635
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/875635 | Method of using controlled resist footing on silicon nitride substrate for smaller spacing of integrated circuit device features | Jun 5, 2001 | Issued |
Array
(
[id] => 1520774
[patent_doc_number] => 06413885
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-07-02
[patent_title] => 'Method for patterning semiconductor devices on a silicon substrate using oxynitride film'
[patent_app_type] => B1
[patent_app_number] => 09/865923
[patent_app_country] => US
[patent_app_date] => 2001-05-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 2316
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/413/06413885.pdf
[firstpage_image] =>[orig_patent_app_number] => 09865923
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/865923 | Method for patterning semiconductor devices on a silicon substrate using oxynitride film | May 28, 2001 | Issued |
Array
(
[id] => 1347661
[patent_doc_number] => 06579812
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-06-17
[patent_title] => 'Method for removing residual polymer after the dry etching process and reducing oxide loss'
[patent_app_type] => B2
[patent_app_number] => 09/861566
[patent_app_country] => US
[patent_app_date] => 2001-05-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 2333
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/579/06579812.pdf
[firstpage_image] =>[orig_patent_app_number] => 09861566
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/861566 | Method for removing residual polymer after the dry etching process and reducing oxide loss | May 21, 2001 | Issued |
Array
(
[id] => 1332735
[patent_doc_number] => 06596653
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-07-22
[patent_title] => 'Hydrogen assisted undoped silicon oxide deposition process for HDP-CVD'
[patent_app_type] => B2
[patent_app_number] => 09/854406
[patent_app_country] => US
[patent_app_date] => 2001-05-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 15
[patent_no_of_words] => 8344
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/596/06596653.pdf
[firstpage_image] =>[orig_patent_app_number] => 09854406
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/854406 | Hydrogen assisted undoped silicon oxide deposition process for HDP-CVD | May 10, 2001 | Issued |
Array
(
[id] => 7078549
[patent_doc_number] => 20010041407
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-11-15
[patent_title] => 'Trench-gate semiconductor devices'
[patent_app_type] => new
[patent_app_number] => 09/854395
[patent_app_country] => US
[patent_app_date] => 2001-05-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 8718
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 13
[patent_words_short_claim] => 29
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0041/20010041407.pdf
[firstpage_image] =>[orig_patent_app_number] => 09854395
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/854395 | Trench-gate semiconductor devices | May 10, 2001 | Issued |