Search

Lisa P Lichtenstein

Examiner (ID: 16977)

Most Active Art Unit
2911
Art Unit(s)
2911, 2902, 2917, 2901, 2916
Total Applications
5523
Issued Applications
5433
Pending Applications
1
Abandoned Applications
89

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12046238 [patent_doc_number] => 09823840 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-11-21 [patent_title] => 'Data volume placement techniques' [patent_app_type] => utility [patent_app_number] => 13/466022 [patent_app_country] => US [patent_app_date] => 2012-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 14983 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13466022 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/466022
Data volume placement techniques May 6, 2012 Issued
Array ( [id] => 8504467 [patent_doc_number] => 20120303875 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-29 [patent_title] => 'POPULATING STRIDES OF TRACKS TO DEMOTE FROM A FIRST CACHE TO A SECOND CACHE' [patent_app_type] => utility [patent_app_number] => 13/465717 [patent_app_country] => US [patent_app_date] => 2012-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7750 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13465717 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/465717
Populating strides of tracks to demote from a first cache to a second cache May 6, 2012 Issued
Array ( [id] => 8504485 [patent_doc_number] => 20120303893 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-29 [patent_title] => 'WRITING OF DATA OF A FIRST BLOCK SIZE IN A RAID ARRAY THAT STORES AND MIRRORS DATA IN A SECOND BLOCK SIZE' [patent_app_type] => utility [patent_app_number] => 13/463122 [patent_app_country] => US [patent_app_date] => 2012-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6054 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13463122 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/463122
Writing of data of a first block size in a raid array that stores and mirrors data in a second block size May 2, 2012 Issued
Array ( [id] => 8504484 [patent_doc_number] => 20120303892 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-29 [patent_title] => 'WRITING OF NEW DATA OF A FIRST BLOCK SIZE IN A RAID ARRAY THAT STORES BOTH PARITY AND DATA IN A SECOND BLOCK SIZE' [patent_app_type] => utility [patent_app_number] => 13/460493 [patent_app_country] => US [patent_app_date] => 2012-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6872 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13460493 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/460493
Writing of new data of a first block size in a raid array that stores both parity and data in a second block size Apr 29, 2012 Issued
Array ( [id] => 9507003 [patent_doc_number] => 08745332 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-03 [patent_title] => 'Cache management of tracks in a first cache and a second cache for a storage' [patent_app_type] => utility [patent_app_number] => 13/456011 [patent_app_country] => US [patent_app_date] => 2012-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 5941 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13456011 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/456011
Cache management of tracks in a first cache and a second cache for a storage Apr 24, 2012 Issued
Array ( [id] => 9680445 [patent_doc_number] => 08819372 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-26 [patent_title] => 'Preventing data loss during reboot and logical storage resource management device' [patent_app_type] => utility [patent_app_number] => 14/005148 [patent_app_country] => US [patent_app_date] => 2012-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3465 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14005148 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/005148
Preventing data loss during reboot and logical storage resource management device Mar 30, 2012 Issued
Array ( [id] => 10644355 [patent_doc_number] => 09361226 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-07 [patent_title] => 'Adjusting a memory transfer setting with large main memory capacity' [patent_app_type] => utility [patent_app_number] => 13/428969 [patent_app_country] => US [patent_app_date] => 2012-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6816 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13428969 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/428969
Adjusting a memory transfer setting with large main memory capacity Mar 22, 2012 Issued
Array ( [id] => 8619294 [patent_doc_number] => 20130024606 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-24 [patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/428507 [patent_app_country] => US [patent_app_date] => 2012-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8229 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13428507 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/428507
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE Mar 22, 2012 Abandoned
Array ( [id] => 8588586 [patent_doc_number] => 20130007407 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'Extending Processor MMU for Shared Address Spaces' [patent_app_type] => utility [patent_app_number] => 13/427881 [patent_app_country] => US [patent_app_date] => 2012-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4288 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13427881 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/427881
Extending processor MMU for shared address spaces Mar 22, 2012 Issued
Array ( [id] => 8443441 [patent_doc_number] => 20120260058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-11 [patent_title] => 'MEMORY MANAGEMENT APPARATUS, MEMORY MANAGEMENT METHOD, AND CONTROL PROGRAM' [patent_app_type] => utility [patent_app_number] => 13/428793 [patent_app_country] => US [patent_app_date] => 2012-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8459 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13428793 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/428793
MEMORY MANAGEMENT APPARATUS, MEMORY MANAGEMENT METHOD, AND CONTROL PROGRAM Mar 22, 2012 Abandoned
Array ( [id] => 8418903 [patent_doc_number] => 20120246402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-27 [patent_title] => 'COMMUNICATION DEVICE, COMMUNICATION METHOD, AND COMPUTER- READABLE RECORDING MEDIUM STORING PROGRAM' [patent_app_type] => utility [patent_app_number] => 13/429140 [patent_app_country] => US [patent_app_date] => 2012-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7922 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13429140 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/429140
COMMUNICATION DEVICE, COMMUNICATION METHOD, AND COMPUTER- READABLE RECORDING MEDIUM STORING PROGRAM Mar 22, 2012 Abandoned
Array ( [id] => 8722580 [patent_doc_number] => 20130073797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-21 [patent_title] => 'MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/428472 [patent_app_country] => US [patent_app_date] => 2012-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8751 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13428472 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/428472
MEMORY DEVICE Mar 22, 2012 Abandoned
Array ( [id] => 8504461 [patent_doc_number] => 20120303869 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-29 [patent_title] => 'HANDLING HIGH PRIROITY REQUESTS IN A SEQUENTIAL ACCESS STORAGE DEVICE HAVING A NON-VOLATILE STORAGE CACHE' [patent_app_type] => utility [patent_app_number] => 13/411159 [patent_app_country] => US [patent_app_date] => 2012-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9786 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13411159 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/411159
Handling high priority requests in a sequential access storage device having a non-volatile storage cache Mar 1, 2012 Issued
Array ( [id] => 11724260 [patent_doc_number] => 09697115 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-04 [patent_title] => 'Segmented caches' [patent_app_type] => utility [patent_app_number] => 14/353862 [patent_app_country] => US [patent_app_date] => 2011-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6361 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14353862 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/353862
Segmented caches Oct 25, 2011 Issued
Array ( [id] => 8893648 [patent_doc_number] => 20130166832 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-27 [patent_title] => 'METHODS AND ELECTRONIC DEVICES FOR ADJUSTING THE OPERATING FREQUENCY OF A MEMORY' [patent_app_type] => utility [patent_app_number] => 13/821700 [patent_app_country] => US [patent_app_date] => 2011-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5335 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13821700 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/821700
Methods and electronic devices for adjusting the operating frequency of a memory Sep 4, 2011 Issued
Array ( [id] => 8893648 [patent_doc_number] => 20130166832 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-27 [patent_title] => 'METHODS AND ELECTRONIC DEVICES FOR ADJUSTING THE OPERATING FREQUENCY OF A MEMORY' [patent_app_type] => utility [patent_app_number] => 13/821700 [patent_app_country] => US [patent_app_date] => 2011-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5335 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13821700 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/821700
Methods and electronic devices for adjusting the operating frequency of a memory Sep 4, 2011 Issued
Array ( [id] => 8893648 [patent_doc_number] => 20130166832 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-27 [patent_title] => 'METHODS AND ELECTRONIC DEVICES FOR ADJUSTING THE OPERATING FREQUENCY OF A MEMORY' [patent_app_type] => utility [patent_app_number] => 13/821700 [patent_app_country] => US [patent_app_date] => 2011-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5335 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13821700 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/821700
Methods and electronic devices for adjusting the operating frequency of a memory Sep 4, 2011 Issued
Array ( [id] => 8893648 [patent_doc_number] => 20130166832 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-27 [patent_title] => 'METHODS AND ELECTRONIC DEVICES FOR ADJUSTING THE OPERATING FREQUENCY OF A MEMORY' [patent_app_type] => utility [patent_app_number] => 13/821700 [patent_app_country] => US [patent_app_date] => 2011-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5335 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13821700 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/821700
Methods and electronic devices for adjusting the operating frequency of a memory Sep 4, 2011 Issued
Array ( [id] => 8517960 [patent_doc_number] => 20120317368 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-13 [patent_title] => 'Memory interface control' [patent_app_type] => utility [patent_app_number] => 13/067602 [patent_app_country] => US [patent_app_date] => 2011-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5369 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13067602 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/067602
Memory interface control Jun 12, 2011 Issued
Array ( [id] => 7664955 [patent_doc_number] => 20110314224 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-22 [patent_title] => 'Apparatus and method for handling access operations issued to local cache structures within a data processing apparatus' [patent_app_type] => utility [patent_app_number] => 13/067491 [patent_app_country] => US [patent_app_date] => 2011-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8711 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13067491 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/067491
Apparatus and method for handling access operations issued to local cache structures within a data processing apparatus Jun 2, 2011 Issued
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