Search

Lisa S. Park

Examiner (ID: 4161)

Most Active Art Unit
1729
Art Unit(s)
1729
Total Applications
793
Issued Applications
550
Pending Applications
105
Abandoned Applications
172

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19206274 [patent_doc_number] => 20240178173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => CHIP PACKAGE STRUCTURE AND CHIP STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/429789 [patent_app_country] => US [patent_app_date] => 2024-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9265 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18429789 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/429789
Chip structure Jan 31, 2024 Issued
Array ( [id] => 19161196 [patent_doc_number] => 20240153903 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => FLIP CHIP PACKAGE ASSEMBLY [patent_app_type] => utility [patent_app_number] => 18/414125 [patent_app_country] => US [patent_app_date] => 2024-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6991 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18414125 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/414125
FLIP CHIP PACKAGE ASSEMBLY Jan 15, 2024 Pending
Array ( [id] => 19146380 [patent_doc_number] => 20240145410 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => MOISTURE HERMETIC GUARD RING FOR SEMICONDUCTOR ON INSULATOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/404708 [patent_app_country] => US [patent_app_date] => 2024-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13464 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18404708 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/404708
Moisture hermetic guard ring for semiconductor on insulator devices Jan 3, 2024 Issued
Array ( [id] => 19146380 [patent_doc_number] => 20240145410 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => MOISTURE HERMETIC GUARD RING FOR SEMICONDUCTOR ON INSULATOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/404708 [patent_app_country] => US [patent_app_date] => 2024-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13464 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18404708 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/404708
Moisture hermetic guard ring for semiconductor on insulator devices Jan 3, 2024 Issued
Array ( [id] => 19146380 [patent_doc_number] => 20240145410 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => MOISTURE HERMETIC GUARD RING FOR SEMICONDUCTOR ON INSULATOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/404708 [patent_app_country] => US [patent_app_date] => 2024-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13464 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18404708 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/404708
Moisture hermetic guard ring for semiconductor on insulator devices Jan 3, 2024 Issued
Array ( [id] => 19131085 [patent_doc_number] => 20240136438 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-25 [patent_title] => INNER SPACERS FOR GATE-ALL-AROUND SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/395058 [patent_app_country] => US [patent_app_date] => 2023-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9680 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18395058 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/395058
Inner spacers for gate-all-around semiconductor devices Dec 21, 2023 Issued
Array ( [id] => 19131085 [patent_doc_number] => 20240136438 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-25 [patent_title] => INNER SPACERS FOR GATE-ALL-AROUND SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/395058 [patent_app_country] => US [patent_app_date] => 2023-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9680 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18395058 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/395058
Inner spacers for gate-all-around semiconductor devices Dec 21, 2023 Issued
Array ( [id] => 19086319 [patent_doc_number] => 20240113120 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => COMPLEMENTARY TRANSISTOR AND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/540524 [patent_app_country] => US [patent_app_date] => 2023-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22292 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18540524 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/540524
COMPLEMENTARY TRANSISTOR AND SEMICONDUCTOR DEVICE Dec 13, 2023 Pending
Array ( [id] => 19086319 [patent_doc_number] => 20240113120 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => COMPLEMENTARY TRANSISTOR AND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/540524 [patent_app_country] => US [patent_app_date] => 2023-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22292 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18540524 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/540524
COMPLEMENTARY TRANSISTOR AND SEMICONDUCTOR DEVICE Dec 13, 2023 Pending
Array ( [id] => 19082356 [patent_doc_number] => 20240109157 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => SOLDER JOINT [patent_app_type] => utility [patent_app_number] => 18/535342 [patent_app_country] => US [patent_app_date] => 2023-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13423 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18535342 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/535342
Solder joint Dec 10, 2023 Issued
Array ( [id] => 19966644 [patent_doc_number] => 12336181 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-17 [patent_title] => Three-dimensional memory device having source-select-gate cut structures and methods for forming the same [patent_app_type] => utility [patent_app_number] => 18/518798 [patent_app_country] => US [patent_app_date] => 2023-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 16404 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18518798 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/518798
Three-dimensional memory device having source-select-gate cut structures and methods for forming the same Nov 23, 2023 Issued
Array ( [id] => 19038265 [patent_doc_number] => 20240088080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => ELECTROPLATED INDIUM BUMP STACKS FOR CRYOGENIC ELECTRONICS [patent_app_type] => utility [patent_app_number] => 18/514466 [patent_app_country] => US [patent_app_date] => 2023-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6337 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18514466 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/514466
Electroplated indium bump stacks for cryogenic electronics Nov 19, 2023 Issued
Array ( [id] => 20175983 [patent_doc_number] => 12394740 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-19 [patent_title] => Solder based hybrid bonding for fine pitch and thin BLT interconnection [patent_app_type] => utility [patent_app_number] => 18/502389 [patent_app_country] => US [patent_app_date] => 2023-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 0 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18502389 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/502389
Solder based hybrid bonding for fine pitch and thin BLT interconnection Nov 5, 2023 Issued
Array ( [id] => 20111564 [patent_doc_number] => 12362300 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Electronic substrate and electronic device [patent_app_type] => utility [patent_app_number] => 18/489871 [patent_app_country] => US [patent_app_date] => 2023-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18489871 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/489871
Electronic substrate and electronic device Oct 18, 2023 Issued
Array ( [id] => 19766042 [patent_doc_number] => 12224345 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 18/489389 [patent_app_country] => US [patent_app_date] => 2023-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 31 [patent_no_of_words] => 7032 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18489389 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/489389
Semiconductor device Oct 17, 2023 Issued
Array ( [id] => 20204131 [patent_doc_number] => 12406915 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-02 [patent_title] => Plated metal layer in power packages [patent_app_type] => utility [patent_app_number] => 18/484310 [patent_app_country] => US [patent_app_date] => 2023-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 0 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18484310 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/484310
Plated metal layer in power packages Oct 9, 2023 Issued
Array ( [id] => 20267073 [patent_doc_number] => 12438072 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Multilayer package substrate with stress buffer [patent_app_type] => utility [patent_app_number] => 18/482944 [patent_app_country] => US [patent_app_date] => 2023-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 0 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18482944 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/482944
Multilayer package substrate with stress buffer Oct 8, 2023 Issued
Array ( [id] => 20267073 [patent_doc_number] => 12438072 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Multilayer package substrate with stress buffer [patent_app_type] => utility [patent_app_number] => 18/482944 [patent_app_country] => US [patent_app_date] => 2023-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 0 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18482944 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/482944
Multilayer package substrate with stress buffer Oct 8, 2023 Issued
Array ( [id] => 20267073 [patent_doc_number] => 12438072 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Multilayer package substrate with stress buffer [patent_app_type] => utility [patent_app_number] => 18/482944 [patent_app_country] => US [patent_app_date] => 2023-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 0 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18482944 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/482944
Multilayer package substrate with stress buffer Oct 8, 2023 Issued
Array ( [id] => 18927209 [patent_doc_number] => 20240030213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => HYBRID MANUFACTURING FOR INTEGRATED CIRCUIT DEVICES AND ASSEMBLIES [patent_app_type] => utility [patent_app_number] => 18/474275 [patent_app_country] => US [patent_app_date] => 2023-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 46924 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18474275 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/474275
Hybrid manufacturing for integrated circuit devices and assemblies Sep 25, 2023 Issued
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