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Lisa S. Park

Examiner (ID: 4161)

Most Active Art Unit
1729
Art Unit(s)
1729
Total Applications
793
Issued Applications
550
Pending Applications
105
Abandoned Applications
172

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19610966 [patent_doc_number] => 12159847 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-03 [patent_title] => Integrated fan-out structures and methods for forming the same [patent_app_type] => utility [patent_app_number] => 17/868226 [patent_app_country] => US [patent_app_date] => 2022-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5573 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17868226 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/868226
Integrated fan-out structures and methods for forming the same Jul 18, 2022 Issued
Array ( [id] => 18906143 [patent_doc_number] => 20240021628 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => DISPLAY PANEL AND MANUFACTURING METHOD THEREOF, AND ELECTRONIC TERMINAL [patent_app_type] => utility [patent_app_number] => 17/796657 [patent_app_country] => US [patent_app_date] => 2022-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8800 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17796657 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/796657
Display panel and manufacturing method thereof, and electronic terminal Jul 12, 2022 Issued
Array ( [id] => 19081117 [patent_doc_number] => 11950513 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-02 [patent_title] => Semiconductor device and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 17/857185 [patent_app_country] => US [patent_app_date] => 2022-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3151 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17857185 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/857185
Semiconductor device and method for fabricating the same Jul 4, 2022 Issued
Array ( [id] => 18883031 [patent_doc_number] => 20240006400 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => LIQUID METAL BASED FIRST LEVEL INTERCONNECTS [patent_app_type] => utility [patent_app_number] => 17/856965 [patent_app_country] => US [patent_app_date] => 2022-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10405 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17856965 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/856965
LIQUID METAL BASED FIRST LEVEL INTERCONNECTS Jul 1, 2022 Pending
Array ( [id] => 19567807 [patent_doc_number] => 12142586 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-12 [patent_title] => Efficient redistribution layer topology [patent_app_type] => utility [patent_app_number] => 17/809854 [patent_app_country] => US [patent_app_date] => 2022-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 5143 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17809854 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/809854
Efficient redistribution layer topology Jun 28, 2022 Issued
Array ( [id] => 17933441 [patent_doc_number] => 20220328567 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => LIGHT-EMITTING DIODE DISPLAY PANEL, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/853325 [patent_app_country] => US [patent_app_date] => 2022-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17273 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17853325 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/853325
Light-emitting diode display panel, manufacturing method thereof, and display device Jun 28, 2022 Issued
Array ( [id] => 17933300 [patent_doc_number] => 20220328426 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => DEVICES AND METHODS FOR REDUCING STRESS ON CIRCUIT COMPONENTS [patent_app_type] => utility [patent_app_number] => 17/850932 [patent_app_country] => US [patent_app_date] => 2022-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6136 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17850932 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/850932
Devices and methods for reducing stress on circuit components Jun 26, 2022 Issued
Array ( [id] => 19943605 [patent_doc_number] => 12315741 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Method of manufacturing electronic device with reduced substrate warpage [patent_app_type] => utility [patent_app_number] => 17/850999 [patent_app_country] => US [patent_app_date] => 2022-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 0 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17850999 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/850999
Method of manufacturing electronic device with reduced substrate warpage Jun 26, 2022 Issued
Array ( [id] => 18688461 [patent_doc_number] => 11784207 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-10 [patent_title] => Method for forming an image sensor [patent_app_type] => utility [patent_app_number] => 17/843088 [patent_app_country] => US [patent_app_date] => 2022-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 27 [patent_no_of_words] => 12970 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17843088 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/843088
Method for forming an image sensor Jun 16, 2022 Issued
Array ( [id] => 19783284 [patent_doc_number] => 12232339 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-18 [patent_title] => Nanomaterial, preparation method thereof, and semiconductor device [patent_app_type] => utility [patent_app_number] => 17/838701 [patent_app_country] => US [patent_app_date] => 2022-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5471 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17838701 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/838701
Nanomaterial, preparation method thereof, and semiconductor device Jun 12, 2022 Issued
Array ( [id] => 19957365 [patent_doc_number] => 12327784 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-10 [patent_title] => Semiconductor package [patent_app_type] => utility [patent_app_number] => 17/839413 [patent_app_country] => US [patent_app_date] => 2022-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17839413 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/839413
Semiconductor package Jun 12, 2022 Issued
Array ( [id] => 19063155 [patent_doc_number] => 11942406 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-26 [patent_title] => Semiconductor packages with embedded interconnects [patent_app_type] => utility [patent_app_number] => 17/834426 [patent_app_country] => US [patent_app_date] => 2022-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 26 [patent_no_of_words] => 10103 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17834426 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/834426
Semiconductor packages with embedded interconnects Jun 6, 2022 Issued
Array ( [id] => 19840255 [patent_doc_number] => 12252627 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-18 [patent_title] => Photosensitive resin composition, film prepared from the same, and electronic apparatus including the film [patent_app_type] => utility [patent_app_number] => 17/805008 [patent_app_country] => US [patent_app_date] => 2022-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 20586 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17805008 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/805008
Photosensitive resin composition, film prepared from the same, and electronic apparatus including the film May 31, 2022 Issued
Array ( [id] => 19720374 [patent_doc_number] => 12205918 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => Submodule semiconductor package [patent_app_type] => utility [patent_app_number] => 17/664749 [patent_app_country] => US [patent_app_date] => 2022-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4528 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17664749 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/664749
Submodule semiconductor package May 23, 2022 Issued
Array ( [id] => 18812570 [patent_doc_number] => 20230386907 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => DIELECTRIC SILICON NITRIDE BARRIER DEPOSITION PROCESS FOR IMPROVED METAL LEAKAGE AND ADHESION [patent_app_type] => utility [patent_app_number] => 17/751976 [patent_app_country] => US [patent_app_date] => 2022-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5641 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17751976 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/751976
Dielectric silicon nitride barrier deposition process for improved metal leakage and adhesion May 23, 2022 Issued
Array ( [id] => 18789454 [patent_doc_number] => 20230378124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => MICROELECTRONIC ASSEMBLY WITH UNDERFILL FLOW CONTROL [patent_app_type] => utility [patent_app_number] => 17/750825 [patent_app_country] => US [patent_app_date] => 2022-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14127 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17750825 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/750825
MICROELECTRONIC ASSEMBLY WITH UNDERFILL FLOW CONTROL May 22, 2022 Pending
Array ( [id] => 18789454 [patent_doc_number] => 20230378124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => MICROELECTRONIC ASSEMBLY WITH UNDERFILL FLOW CONTROL [patent_app_type] => utility [patent_app_number] => 17/750825 [patent_app_country] => US [patent_app_date] => 2022-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14127 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17750825 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/750825
MICROELECTRONIC ASSEMBLY WITH UNDERFILL FLOW CONTROL May 22, 2022 Pending
Array ( [id] => 20259054 [patent_doc_number] => 12431418 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => Three dimensional semiconductor trace length matching and associated systems and methods [patent_app_type] => utility [patent_app_number] => 17/750140 [patent_app_country] => US [patent_app_date] => 2022-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 2263 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17750140 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/750140
Three dimensional semiconductor trace length matching and associated systems and methods May 19, 2022 Issued
Array ( [id] => 19507886 [patent_doc_number] => 12119316 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-15 [patent_title] => Patterned and planarized under-bump metallization [patent_app_type] => utility [patent_app_number] => 17/664113 [patent_app_country] => US [patent_app_date] => 2022-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 6732 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17664113 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/664113
Patterned and planarized under-bump metallization May 18, 2022 Issued
Array ( [id] => 18024455 [patent_doc_number] => 20220375954 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => INTEGRATED CIRCUIT COMPRISING AT LEAST ONE BIPOLAR TRANSISTOR AND A CORRESPONDING METHOD OF PRODUCTION [patent_app_type] => utility [patent_app_number] => 17/747540 [patent_app_country] => US [patent_app_date] => 2022-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5702 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17747540 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/747540
Integrated circuit comprising at least one bipolar transistor and a corresponding method of production May 17, 2022 Issued
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