Search

Lisa Solomon

Examiner (ID: 2253)

Most Active Art Unit
2853
Art Unit(s)
2861, 2853
Total Applications
1587
Issued Applications
1416
Pending Applications
96
Abandoned Applications
112

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18982543 [patent_doc_number] => 11907721 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Inserting predefined pad values into a stream of vectors [patent_app_type] => utility [patent_app_number] => 17/379528 [patent_app_country] => US [patent_app_date] => 2021-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 49 [patent_no_of_words] => 36712 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17379528 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/379528
Inserting predefined pad values into a stream of vectors Jul 18, 2021 Issued
Array ( [id] => 18234932 [patent_doc_number] => 11599491 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-07 [patent_title] => System on chip having semaphore function and method for implementing semaphore function [patent_app_type] => utility [patent_app_number] => 17/376590 [patent_app_country] => US [patent_app_date] => 2021-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12313 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17376590 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/376590
System on chip having semaphore function and method for implementing semaphore function Jul 14, 2021 Issued
Array ( [id] => 18826532 [patent_doc_number] => 11841808 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-12 [patent_title] => System and method for processing requests in a multithreaded system [patent_app_type] => utility [patent_app_number] => 17/375499 [patent_app_country] => US [patent_app_date] => 2021-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9033 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17375499 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/375499
System and method for processing requests in a multithreaded system Jul 13, 2021 Issued
Array ( [id] => 17187218 [patent_doc_number] => 20210334103 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => NESTED LOOP CONTROL [patent_app_type] => utility [patent_app_number] => 17/367384 [patent_app_country] => US [patent_app_date] => 2021-07-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13163 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17367384 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/367384
Nested loop control Jul 3, 2021 Issued
Array ( [id] => 18330721 [patent_doc_number] => 11635963 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-25 [patent_title] => Address manipulation using indices and tags [patent_app_type] => utility [patent_app_number] => 17/364718 [patent_app_country] => US [patent_app_date] => 2021-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 12453 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17364718 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/364718
Address manipulation using indices and tags Jun 29, 2021 Issued
Array ( [id] => 18095700 [patent_doc_number] => 20220414041 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => HIGH BIT RATE COMMUNICATION INTERFACE WITH COMMON MODE VOLTAGE ADJUSTMENT [patent_app_type] => utility [patent_app_number] => 17/362060 [patent_app_country] => US [patent_app_date] => 2021-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6898 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17362060 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/362060
High bit rate communication interface with common mode voltage adjustment Jun 28, 2021 Issued
Array ( [id] => 18095841 [patent_doc_number] => 20220414182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => APPARATUSES, METHODS, AND SYSTEMS FOR INSTRUCTIONS FOR MATRIX MULTIPLICATION INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 17/359519 [patent_app_country] => US [patent_app_date] => 2021-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22294 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17359519 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/359519
Apparatuses, methods, and systems for instructions for matrix multiplication instructions Jun 25, 2021 Issued
Array ( [id] => 19719362 [patent_doc_number] => 12204901 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => Cache support for indirect loads and indirect stores in graph applications [patent_app_type] => utility [patent_app_number] => 17/359305 [patent_app_country] => US [patent_app_date] => 2021-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 27 [patent_no_of_words] => 15235 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17359305 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/359305
Cache support for indirect loads and indirect stores in graph applications Jun 24, 2021 Issued
Array ( [id] => 18095510 [patent_doc_number] => 20220413851 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => REGISTER FILE FOR SYSTOLIC ARRAY [patent_app_type] => utility [patent_app_number] => 17/304794 [patent_app_country] => US [patent_app_date] => 2021-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 50295 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17304794 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/304794
Register file for systolic array Jun 24, 2021 Issued
Array ( [id] => 17143723 [patent_doc_number] => 20210311736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-07 [patent_title] => VECTOR BIT TRANSPOSE [patent_app_type] => utility [patent_app_number] => 17/353908 [patent_app_country] => US [patent_app_date] => 2021-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9778 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17353908 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/353908
Vector bit transpose Jun 21, 2021 Issued
Array ( [id] => 17337825 [patent_doc_number] => 20220004156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-06 [patent_title] => INDUSTRIAL CONTROL SYSTEM HAVING MULTI-LAYERED CONTROL LOGIC EXECUTION [patent_app_type] => utility [patent_app_number] => 17/352779 [patent_app_country] => US [patent_app_date] => 2021-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2341 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17352779 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/352779
Industrial control system having multi-layered control logic execution Jun 20, 2021 Issued
Array ( [id] => 17956149 [patent_doc_number] => 11482262 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-10-25 [patent_title] => Per pin Vref for data receivers in non-volatile memory system [patent_app_type] => utility [patent_app_number] => 17/348904 [patent_app_country] => US [patent_app_date] => 2021-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 13620 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17348904 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/348904
Per pin Vref for data receivers in non-volatile memory system Jun 15, 2021 Issued
Array ( [id] => 18291289 [patent_doc_number] => 11620159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-04 [patent_title] => Systems and methods for I/O command scheduling based on multiple resource parameters [patent_app_type] => utility [patent_app_number] => 17/333316 [patent_app_country] => US [patent_app_date] => 2021-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 9004 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17333316 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/333316
Systems and methods for I/O command scheduling based on multiple resource parameters May 27, 2021 Issued
Array ( [id] => 18386226 [patent_doc_number] => 11657007 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-23 [patent_title] => Remote memory selection [patent_app_type] => utility [patent_app_number] => 17/333420 [patent_app_country] => US [patent_app_date] => 2021-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6152 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17333420 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/333420
Remote memory selection May 27, 2021 Issued
Array ( [id] => 17690541 [patent_doc_number] => 20220197834 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => DATA TRANSMISSION METHOD FOR CONVOLUTION OPERATION, FETCHER, AND CONVOLUTION OPERATION APPARATUS [patent_app_type] => utility [patent_app_number] => 17/330229 [patent_app_country] => US [patent_app_date] => 2021-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7171 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17330229 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/330229
Data transmission method for convolution operation, fetcher, and convolution operation apparatus May 24, 2021 Issued
Array ( [id] => 17550240 [patent_doc_number] => 20220121582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => MEMORY DEVICE SUPPORTING A HIGH-EFFICIENT INPUT/OUTPUT INTERFACE AND A MEMORY SYSTEM INCLUDING THE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/326513 [patent_app_country] => US [patent_app_date] => 2021-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18664 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17326513 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/326513
Memory device supporting a high-efficient input/output interface and a memory system including the memory device May 20, 2021 Issued
Array ( [id] => 17824597 [patent_doc_number] => 11429545 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-30 [patent_title] => Method and apparatus for data reads in host performance acceleration mode [patent_app_type] => utility [patent_app_number] => 17/324762 [patent_app_country] => US [patent_app_date] => 2021-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8414 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17324762 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/324762
Method and apparatus for data reads in host performance acceleration mode May 18, 2021 Issued
Array ( [id] => 17862318 [patent_doc_number] => 11443479 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-09-13 [patent_title] => Snapshot arbitration techniques for memory requests [patent_app_type] => utility [patent_app_number] => 17/324857 [patent_app_country] => US [patent_app_date] => 2021-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 9447 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17324857 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/324857
Snapshot arbitration techniques for memory requests May 18, 2021 Issued
Array ( [id] => 20130894 [patent_doc_number] => 12373207 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-29 [patent_title] => Implementing a micro-operation cache with compaction [patent_app_type] => utility [patent_app_number] => 17/325067 [patent_app_country] => US [patent_app_date] => 2021-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1158 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17325067 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/325067
Implementing a micro-operation cache with compaction May 18, 2021 Issued
Array ( [id] => 18136233 [patent_doc_number] => 11561912 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-24 [patent_title] => Host controller interface using multiple circular queue, and operating method thereof [patent_app_type] => utility [patent_app_number] => 17/321916 [patent_app_country] => US [patent_app_date] => 2021-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 28971 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17321916 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/321916
Host controller interface using multiple circular queue, and operating method thereof May 16, 2021 Issued
Menu