
Lisa Solomon
Examiner (ID: 2253)
| Most Active Art Unit | 2853 |
| Art Unit(s) | 2861, 2853 |
| Total Applications | 1587 |
| Issued Applications | 1416 |
| Pending Applications | 96 |
| Abandoned Applications | 112 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 16346151
[patent_doc_number] => 20200310802
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-10-01
[patent_title] => APPARATUSES, METHODS, AND SYSTEMS FOR HASHING INSTRUCTIONS
[patent_app_type] => utility
[patent_app_number] => 16/370459
[patent_app_country] => US
[patent_app_date] => 2019-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 29083
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 229
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16370459
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/370459 | Apparatuses, methods, and systems for hashing instructions | Mar 28, 2019 | Issued |
Array
(
[id] => 16346144
[patent_doc_number] => 20200310795
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-10-01
[patent_title] => ARRAY BROADCAST AND REDUCTION SYSTEMS AND METHODS
[patent_app_type] => utility
[patent_app_number] => 16/369846
[patent_app_country] => US
[patent_app_date] => 2019-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 24958
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -23
[patent_words_short_claim] => 173
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16369846
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/369846 | Array broadcast and reduction systems and methods | Mar 28, 2019 | Issued |
Array
(
[id] => 16706228
[patent_doc_number] => 10956160
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-03-23
[patent_title] => Method and apparatus for a multi-level reservation station with instruction recirculation
[patent_app_type] => utility
[patent_app_number] => 16/367171
[patent_app_country] => US
[patent_app_date] => 2019-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 13
[patent_no_of_words] => 9605
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16367171
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/367171 | Method and apparatus for a multi-level reservation station with instruction recirculation | Mar 26, 2019 | Issued |
Array
(
[id] => 16278741
[patent_doc_number] => 10761771
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-09-01
[patent_title] => Memory system and method for controlling nonvolatile memory
[patent_app_type] => utility
[patent_app_number] => 16/351993
[patent_app_country] => US
[patent_app_date] => 2019-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 24
[patent_no_of_words] => 21881
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 176
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16351993
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/351993 | Memory system and method for controlling nonvolatile memory | Mar 12, 2019 | Issued |
Array
(
[id] => 16844678
[patent_doc_number] => 11016763
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-05-25
[patent_title] => Implementing a micro-operation cache with compaction
[patent_app_type] => utility
[patent_app_number] => 16/297358
[patent_app_country] => US
[patent_app_date] => 2019-03-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5643
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16297358
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/297358 | Implementing a micro-operation cache with compaction | Mar 7, 2019 | Issued |
Array
(
[id] => 16706234
[patent_doc_number] => 10956166
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-03-23
[patent_title] => Instruction ordering
[patent_app_type] => utility
[patent_app_number] => 16/296507
[patent_app_country] => US
[patent_app_date] => 2019-03-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 12
[patent_no_of_words] => 7249
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16296507
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/296507 | Instruction ordering | Mar 7, 2019 | Issued |
Array
(
[id] => 16706236
[patent_doc_number] => 10956168
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-03-23
[patent_title] => Post completion execution in an out-of-order processor design
[patent_app_type] => utility
[patent_app_number] => 16/296621
[patent_app_country] => US
[patent_app_date] => 2019-03-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5773
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16296621
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/296621 | Post completion execution in an out-of-order processor design | Mar 7, 2019 | Issued |
Array
(
[id] => 14782157
[patent_doc_number] => 20190265976
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-08-29
[patent_title] => Additional Channel for Exchanging Useful Information
[patent_app_type] => utility
[patent_app_number] => 16/283753
[patent_app_country] => US
[patent_app_date] => 2019-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 59647
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16283753
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/283753 | Additional Channel for Exchanging Useful Information | Feb 22, 2019 | Abandoned |
Array
(
[id] => 16431397
[patent_doc_number] => 10831479
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-11-10
[patent_title] => Instruction to move data in a right-to-left direction
[patent_app_type] => utility
[patent_app_number] => 16/280616
[patent_app_country] => US
[patent_app_date] => 2019-02-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 12
[patent_no_of_words] => 8689
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16280616
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/280616 | Instruction to move data in a right-to-left direction | Feb 19, 2019 | Issued |
Array
(
[id] => 16255517
[patent_doc_number] => 20200264891
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-08-20
[patent_title] => CONSTANT SCALAR REGISTER ARCHITECTURE FOR ACCELERATION OF DELAY SENSITIVE ALGORITHM
[patent_app_type] => utility
[patent_app_number] => 16/281052
[patent_app_country] => US
[patent_app_date] => 2019-02-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5271
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16281052
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/281052 | CONSTANT SCALAR REGISTER ARCHITECTURE FOR ACCELERATION OF DELAY SENSITIVE ALGORITHM | Feb 19, 2019 | Abandoned |
Array
(
[id] => 15313161
[patent_doc_number] => 10521285
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-12-31
[patent_title] => Processing system with interspersed processors with multi-layer interconnection
[patent_app_type] => utility
[patent_app_number] => 16/252904
[patent_app_country] => US
[patent_app_date] => 2019-01-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 26
[patent_no_of_words] => 19851
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16252904
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/252904 | Processing system with interspersed processors with multi-layer interconnection | Jan 20, 2019 | Issued |
Array
(
[id] => 14443601
[patent_doc_number] => 20190179674
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-06-13
[patent_title] => SYSTEMS AND METHODS FOR DATA MANAGEMENT
[patent_app_type] => utility
[patent_app_number] => 16/244510
[patent_app_country] => US
[patent_app_date] => 2019-01-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 23032
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16244510
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/244510 | Systems and methods for data management | Jan 9, 2019 | Issued |
Array
(
[id] => 17308990
[patent_doc_number] => 11210100
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-12-28
[patent_title] => Coprocessor operation bundling
[patent_app_type] => utility
[patent_app_number] => 16/242151
[patent_app_country] => US
[patent_app_date] => 2019-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 13948
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16242151
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/242151 | Coprocessor operation bundling | Jan 7, 2019 | Issued |
Array
(
[id] => 15139571
[patent_doc_number] => 10483272
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-11-19
[patent_title] => Electronic device and method for fabricating the same
[patent_app_type] => utility
[patent_app_number] => 16/242320
[patent_app_country] => US
[patent_app_date] => 2019-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 29
[patent_no_of_words] => 15716
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 234
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16242320
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/242320 | Electronic device and method for fabricating the same | Jan 7, 2019 | Issued |
Array
(
[id] => 14282273
[patent_doc_number] => 20190138421
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-05-09
[patent_title] => REAL-TIME HIERARCHICAL PROTOCOL DECODING
[patent_app_type] => utility
[patent_app_number] => 16/241192
[patent_app_country] => US
[patent_app_date] => 2019-01-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7817
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16241192
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/241192 | Real-time hierarchical protocol decoding | Jan 6, 2019 | Issued |
Array
(
[id] => 14689365
[patent_doc_number] => 20190243798
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-08-08
[patent_title] => APPARATUS FOR VIRTUAL CHANNEL ALLOCATION VIA A HIGH SPEED BUS INTERFACE
[patent_app_type] => utility
[patent_app_number] => 16/241781
[patent_app_country] => US
[patent_app_date] => 2019-01-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7951
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16241781
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/241781 | Apparatus for virtual channel allocation via a high speed bus interface | Jan 6, 2019 | Issued |
Array
(
[id] => 16160913
[patent_doc_number] => 20200218689
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-07-09
[patent_title] => PIPELINING MULTI-DIRECTIONAL REDUCTION
[patent_app_type] => utility
[patent_app_number] => 16/241765
[patent_app_country] => US
[patent_app_date] => 2019-01-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7049
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16241765
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/241765 | Pipelining multi-directional reduction | Jan 6, 2019 | Issued |
Array
(
[id] => 15854841
[patent_doc_number] => 10642705
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-05-05
[patent_title] => Storage system and storage method
[patent_app_type] => utility
[patent_app_number] => 16/241289
[patent_app_country] => US
[patent_app_date] => 2019-01-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 9634
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16241289
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/241289 | Storage system and storage method | Jan 6, 2019 | Issued |
Array
(
[id] => 15059103
[patent_doc_number] => 10459857
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-10-29
[patent_title] => Data receiving apparatus, data transmission and reception system, and control method of data transmission and reception system
[patent_app_type] => utility
[patent_app_number] => 16/240840
[patent_app_country] => US
[patent_app_date] => 2019-01-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 14
[patent_no_of_words] => 5819
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16240840
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/240840 | Data receiving apparatus, data transmission and reception system, and control method of data transmission and reception system | Jan 6, 2019 | Issued |
Array
(
[id] => 15982445
[patent_doc_number] => 10671550
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-06-02
[patent_title] => Memory offloading a problem using accelerators
[patent_app_type] => utility
[patent_app_number] => 16/238949
[patent_app_country] => US
[patent_app_date] => 2019-01-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 22
[patent_no_of_words] => 10423
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16238949
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/238949 | Memory offloading a problem using accelerators | Jan 2, 2019 | Issued |