Search

Lisa Solomon

Examiner (ID: 2253)

Most Active Art Unit
2853
Art Unit(s)
2861, 2853
Total Applications
1587
Issued Applications
1416
Pending Applications
96
Abandoned Applications
112

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13797501 [patent_doc_number] => 20190012289 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-10 [patent_title] => CONTROL METHOD FOR TRANSMISSION AND RECEPTION SYSTEM, TRANSMITTING APPARATUS, AND RECEIVING APPARATUS [patent_app_type] => utility [patent_app_number] => 16/017443 [patent_app_country] => US [patent_app_date] => 2018-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8272 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16017443 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/017443
Control method for transmission and reception system, transmitting apparatus, and receiving apparatus Jun 24, 2018 Issued
Array ( [id] => 15297359 [patent_doc_number] => 20190391815 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => INSTRUCTION AGE MATRIX AND LOGIC FOR QUEUES IN A PROCESSOR [patent_app_type] => utility [patent_app_number] => 16/014338 [patent_app_country] => US [patent_app_date] => 2018-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13581 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16014338 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/014338
INSTRUCTION AGE MATRIX AND LOGIC FOR QUEUES IN A PROCESSOR Jun 20, 2018 Abandoned
Array ( [id] => 13432607 [patent_doc_number] => 20180267846 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-20 [patent_title] => Processing System With Interspersed Processors With Multi-Layer Interconnection [patent_app_type] => utility [patent_app_number] => 15/986701 [patent_app_country] => US [patent_app_date] => 2018-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19817 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15986701 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/986701
Processing system with interspersed processors with multi-layer interconnection May 21, 2018 Issued
Array ( [id] => 14825473 [patent_doc_number] => 10409746 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-10 [patent_title] => Memory access control device and control method of memory access [patent_app_type] => utility [patent_app_number] => 15/964250 [patent_app_country] => US [patent_app_date] => 2018-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 4358 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15964250 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/964250
Memory access control device and control method of memory access Apr 26, 2018 Issued
Array ( [id] => 15043119 [patent_doc_number] => 20190332564 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-31 [patent_title] => ACCELERATOR MANAGEMENT [patent_app_type] => utility [patent_app_number] => 15/964115 [patent_app_country] => US [patent_app_date] => 2018-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11299 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15964115 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/964115
Accelerator management Apr 26, 2018 Issued
Array ( [id] => 15043105 [patent_doc_number] => 20190332557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-31 [patent_title] => FLEXIBLE I/O SLOT CONNECTIONS [patent_app_type] => utility [patent_app_number] => 15/963420 [patent_app_country] => US [patent_app_date] => 2018-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10433 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15963420 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/963420
Flexible I/O slot connections Apr 25, 2018 Issued
Array ( [id] => 15043099 [patent_doc_number] => 20190332554 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-31 [patent_title] => TIME DEPENDENT SERVICE LEVEL OBJECTIVES [patent_app_type] => utility [patent_app_number] => 15/963398 [patent_app_country] => US [patent_app_date] => 2018-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12278 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15963398 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/963398
Time dependent service level objectives Apr 25, 2018 Issued
Array ( [id] => 13526247 [patent_doc_number] => 20180314666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-01 [patent_title] => STORAGE SYSTEM [patent_app_type] => utility [patent_app_number] => 15/959675 [patent_app_country] => US [patent_app_date] => 2018-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 33078 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15959675 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/959675
Storage system Apr 22, 2018 Issued
Array ( [id] => 13376371 [patent_doc_number] => 20180239727 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-23 [patent_title] => Secure Access to Peripheral Devices Over a Bus [patent_app_type] => utility [patent_app_number] => 15/955715 [patent_app_country] => US [patent_app_date] => 2018-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7434 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -30 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15955715 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/955715
Secure access to peripheral devices over a bus Apr 17, 2018 Issued
Array ( [id] => 13347207 [patent_doc_number] => 20180225143 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-09 [patent_title] => METHOD AND APPARATUS FOR EXECUTING NON-MASKABLE INTERRUPT [patent_app_type] => utility [patent_app_number] => 15/947491 [patent_app_country] => US [patent_app_date] => 2018-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8602 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15947491 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/947491
Method and apparatus for executing non-maskable interrupt Apr 5, 2018 Issued
Array ( [id] => 13347151 [patent_doc_number] => 20180225115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-09 [patent_title] => SIGNAL PROCESSING CIRCUIT [patent_app_type] => utility [patent_app_number] => 15/943063 [patent_app_country] => US [patent_app_date] => 2018-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13335 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15943063 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/943063
Signal processing circuit Apr 1, 2018 Issued
Array ( [id] => 17121194 [patent_doc_number] => 11132329 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-28 [patent_title] => Electronic control device and method of controlling logic circuit [patent_app_type] => utility [patent_app_number] => 16/606830 [patent_app_country] => US [patent_app_date] => 2018-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 13494 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16606830 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/606830
Electronic control device and method of controlling logic circuit Mar 21, 2018 Issued
Array ( [id] => 17364906 [patent_doc_number] => 11231927 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-25 [patent_title] => System, apparatus and method for providing a fabric for an accelerator [patent_app_type] => utility [patent_app_number] => 15/915476 [patent_app_country] => US [patent_app_date] => 2018-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8194 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15915476 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/915476
System, apparatus and method for providing a fabric for an accelerator Mar 7, 2018 Issued
Array ( [id] => 12845467 [patent_doc_number] => 20180173662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-21 [patent_title] => SYSTEM ON CHIP HAVING SEMAPHORE FUNCTION AND METHOD FOR IMPLEMENTING SEMAPHORE FUNCTION [patent_app_type] => utility [patent_app_number] => 15/899877 [patent_app_country] => US [patent_app_date] => 2018-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12235 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15899877 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/899877
System on chip having semaphore function and method for implementing semaphore function Feb 19, 2018 Issued
Array ( [id] => 13361587 [patent_doc_number] => 20180232333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-16 [patent_title] => METHODS AND APPARATUS FOR VIRTUAL CHANNEL ALLOCATION VIA A HIGH SPEED BUS INTERFACE [patent_app_type] => utility [patent_app_number] => 15/894719 [patent_app_country] => US [patent_app_date] => 2018-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7908 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15894719 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/894719
Methods and apparatus for virtual channel allocation via a high speed bus interface Feb 11, 2018 Issued
Array ( [id] => 14668875 [patent_doc_number] => 10372338 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-06 [patent_title] => Memory controller and data processing circuit with improved system efficiency [patent_app_type] => utility [patent_app_number] => 15/868535 [patent_app_country] => US [patent_app_date] => 2018-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5726 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15868535 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/868535
Memory controller and data processing circuit with improved system efficiency Jan 10, 2018 Issued
Array ( [id] => 15106579 [patent_doc_number] => 10474615 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-12 [patent_title] => Hub [patent_app_type] => utility [patent_app_number] => 15/866462 [patent_app_country] => US [patent_app_date] => 2018-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5426 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15866462 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/866462
Hub Jan 9, 2018 Issued
Array ( [id] => 14571119 [patent_doc_number] => 20190213166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-11 [patent_title] => METHODS AND APPARATUS FOR REDUCED-LATENCY DATA TRANSMISSION WITH AN INTER-PROCESSOR COMMUNICATION LINK BETWEEN INDEPENDENTLY OPERABLE PROCESSORS [patent_app_type] => utility [patent_app_number] => 15/865638 [patent_app_country] => US [patent_app_date] => 2018-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16211 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15865638 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/865638
Methods and apparatus for reduced-latency data transmission with an inter-processor communication link between independently operable processors Jan 8, 2018 Issued
Array ( [id] => 13361569 [patent_doc_number] => 20180232324 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-16 [patent_title] => MULTI-PORT MULTI-SIDEBAND-GPIO CONSOLIDATION TECHNIQUE OVER A MULTI-DROP SERIAL BUS [patent_app_type] => utility [patent_app_number] => 15/864871 [patent_app_country] => US [patent_app_date] => 2018-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13358 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15864871 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/864871
Multi-port multi-sideband-GPIO consolidation technique over a multi-drop serial bus Jan 7, 2018 Issued
Array ( [id] => 15425275 [patent_doc_number] => 10545564 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-28 [patent_title] => Discharge circuit integrated in chip of slave device to follow bus rectifier bridge [patent_app_type] => utility [patent_app_number] => 16/337483 [patent_app_country] => US [patent_app_date] => 2017-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3455 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16337483 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/337483
Discharge circuit integrated in chip of slave device to follow bus rectifier bridge Dec 27, 2017 Issued
Menu