
Lisa Solomon
Examiner (ID: 2253)
| Most Active Art Unit | 2853 |
| Art Unit(s) | 2861, 2853 |
| Total Applications | 1587 |
| Issued Applications | 1416 |
| Pending Applications | 96 |
| Abandoned Applications | 112 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 11651613
[patent_doc_number] => 20170147514
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-05-25
[patent_title] => 'MEMORY MODULE WITH TIMING-CONTROLLED DATA PATHS IN DISTRIBUTED DATA BUFFERS'
[patent_app_type] => utility
[patent_app_number] => 15/426064
[patent_app_country] => US
[patent_app_date] => 2017-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 27
[patent_no_of_words] => 11612
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15426064
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/426064 | Memory module with timing-controlled data paths in distributed data buffers | Feb 6, 2017 | Issued |
Array
(
[id] => 13281481
[patent_doc_number] => 10152325
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-12-11
[patent_title] => Instruction and logic to provide pushing buffer copy and store functionality
[patent_app_type] => utility
[patent_app_number] => 15/426963
[patent_app_country] => US
[patent_app_date] => 2017-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 28
[patent_no_of_words] => 18007
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15426963
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/426963 | Instruction and logic to provide pushing buffer copy and store functionality | Feb 6, 2017 | Issued |
Array
(
[id] => 11875269
[patent_doc_number] => 09747039
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-08-29
[patent_title] => 'Reservations over multiple paths on NVMe over fabrics'
[patent_app_type] => utility
[patent_app_number] => 15/419886
[patent_app_country] => US
[patent_app_date] => 2017-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 17017
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 177
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15419886
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/419886 | Reservations over multiple paths on NVMe over fabrics | Jan 29, 2017 | Issued |
Array
(
[id] => 14298945
[patent_doc_number] => 10289599
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-05-14
[patent_title] => System and method employed for signal reception by providing programmable and switchable line terminations
[patent_app_type] => utility
[patent_app_number] => 15/404217
[patent_app_country] => US
[patent_app_date] => 2017-01-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 2369
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15404217
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/404217 | System and method employed for signal reception by providing programmable and switchable line terminations | Jan 11, 2017 | Issued |
Array
(
[id] => 13752653
[patent_doc_number] => 10169273
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-01-01
[patent_title] => Forced compression of single I2C writes
[patent_app_type] => utility
[patent_app_number] => 15/403559
[patent_app_country] => US
[patent_app_date] => 2017-01-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 12113
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15403559
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/403559 | Forced compression of single I2C writes | Jan 10, 2017 | Issued |
Array
(
[id] => 13174727
[patent_doc_number] => 10103489
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-10-16
[patent_title] => Validating connection, structural characteristics and positioning of cable connectors
[patent_app_type] => utility
[patent_app_number] => 15/401131
[patent_app_country] => US
[patent_app_date] => 2017-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 13
[patent_no_of_words] => 9544
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 200
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15401131
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/401131 | Validating connection, structural characteristics and positioning of cable connectors | Jan 8, 2017 | Issued |
Array
(
[id] => 12032722
[patent_doc_number] => 20170322821
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-11-09
[patent_title] => 'SERVER CAPABLE OF SUPPORTING AND AUTOMATICALLY IDENTIFYING IP HARD DISK AND SATA HARD DISK'
[patent_app_type] => utility
[patent_app_number] => 15/362029
[patent_app_country] => US
[patent_app_date] => 2016-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2366
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15362029
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/362029 | Server capable of supporting and automatically identifying IP hard disk and SATA hard disk | Nov 27, 2016 | Issued |
Array
(
[id] => 12060802
[patent_doc_number] => 20170337146
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-11-23
[patent_title] => 'MEMORY DEVICE, MEMORY CONTROLLER, AND CONTROL METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 15/361474
[patent_app_country] => US
[patent_app_date] => 2016-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3538
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15361474
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/361474 | Memory device, memory controller, and control method thereof | Nov 26, 2016 | Issued |
Array
(
[id] => 12221901
[patent_doc_number] => 20180060262
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-03-01
[patent_title] => 'USB COMMUNICATION CONTROL METHOD FOR USB HOST'
[patent_app_type] => utility
[patent_app_number] => 15/359910
[patent_app_country] => US
[patent_app_date] => 2016-11-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 10273
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15359910
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/359910 | USB communication control method for USB host | Nov 22, 2016 | Issued |
Array
(
[id] => 11501502
[patent_doc_number] => 20170075687
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-03-16
[patent_title] => 'SIGNAL PROCESSING CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 15/360028
[patent_app_country] => US
[patent_app_date] => 2016-11-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 14444
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15360028
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/360028 | Signal processing circuit | Nov 22, 2016 | Issued |
Array
(
[id] => 12756304
[patent_doc_number] => 20180143935
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-05-24
[patent_title] => Bus Device with Programmable Address
[patent_app_type] => utility
[patent_app_number] => 15/360580
[patent_app_country] => US
[patent_app_date] => 2016-11-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9425
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15360580
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/360580 | Bus device with programmable address | Nov 22, 2016 | Issued |
Array
(
[id] => 11933254
[patent_doc_number] => 09800263
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-10-24
[patent_title] => 'Signal processing system and associated method'
[patent_app_type] => utility
[patent_app_number] => 15/358282
[patent_app_country] => US
[patent_app_date] => 2016-11-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 14832
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 178
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15358282
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/358282 | Signal processing system and associated method | Nov 21, 2016 | Issued |
Array
(
[id] => 11458879
[patent_doc_number] => 20170052785
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-02-23
[patent_title] => 'INSTRUCTIONS AND LOGIC TO VECTORIZE CONDITIONAL LOOPS'
[patent_app_type] => utility
[patent_app_number] => 15/344836
[patent_app_country] => US
[patent_app_date] => 2016-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 28
[patent_no_of_words] => 18876
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15344836
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/344836 | Instructions and logic to vectorize conditional loops | Nov 6, 2016 | Issued |
Array
(
[id] => 14395451
[patent_doc_number] => 10311009
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-06-04
[patent_title] => Apparatus and methods for communicatively coupling field devices to controllers in a process control system using a distributed marshaling architecture
[patent_app_type] => utility
[patent_app_number] => 15/332355
[patent_app_country] => US
[patent_app_date] => 2016-10-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 16
[patent_no_of_words] => 22244
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 200
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15332355
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/332355 | Apparatus and methods for communicatively coupling field devices to controllers in a process control system using a distributed marshaling architecture | Oct 23, 2016 | Issued |
Array
(
[id] => 11570520
[patent_doc_number] => 20170109164
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-04-20
[patent_title] => 'PROCESSORS, METHODS, AND SYSTEMS TO IMPLEMENT PARTIAL REGISTER ACCESSES WITH MASKED FULL REGISTER ACCESSES'
[patent_app_type] => utility
[patent_app_number] => 15/331940
[patent_app_country] => US
[patent_app_date] => 2016-10-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 20061
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15331940
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/331940 | Processors, methods, and systems to implement partial register accesses with masked full register accesses | Oct 23, 2016 | Issued |
Array
(
[id] => 11860964
[patent_doc_number] => 09740647
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-08-22
[patent_title] => 'Migrating DMA mappings from a source I/O adapter of a computing system to a destination I/O adapter of the computing system'
[patent_app_type] => utility
[patent_app_number] => 15/299596
[patent_app_country] => US
[patent_app_date] => 2016-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 7505
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15299596
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/299596 | Migrating DMA mappings from a source I/O adapter of a computing system to a destination I/O adapter of the computing system | Oct 20, 2016 | Issued |
Array
(
[id] => 17209430
[patent_doc_number] => 11169802
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-11-09
[patent_title] => Systems, apparatuses, and methods for fused multiply add
[patent_app_type] => utility
[patent_app_number] => 16/338324
[patent_app_country] => US
[patent_app_date] => 2016-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 29
[patent_no_of_words] => 19608
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 197
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16338324
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/338324 | Systems, apparatuses, and methods for fused multiply add | Oct 19, 2016 | Issued |
Array
(
[id] => 13752583
[patent_doc_number] => 10169238
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-01-01
[patent_title] => Memory access for exactly-once messaging
[patent_app_type] => utility
[patent_app_number] => 15/281239
[patent_app_country] => US
[patent_app_date] => 2016-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 6912
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15281239
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/281239 | Memory access for exactly-once messaging | Sep 29, 2016 | Issued |
Array
(
[id] => 14890209
[patent_doc_number] => 10425161
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-09-24
[patent_title] => Circuit arrangement and corresponding method
[patent_app_type] => utility
[patent_app_number] => 15/281767
[patent_app_country] => US
[patent_app_date] => 2016-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 4087
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15281767
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/281767 | Circuit arrangement and corresponding method | Sep 29, 2016 | Issued |
Array
(
[id] => 16032609
[patent_doc_number] => 10678725
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-06-09
[patent_title] => Interface circuit relating to variable delay, and semiconductor apparatus and system including the same
[patent_app_type] => utility
[patent_app_number] => 15/279965
[patent_app_country] => US
[patent_app_date] => 2016-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 12
[patent_no_of_words] => 8554
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15279965
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/279965 | Interface circuit relating to variable delay, and semiconductor apparatus and system including the same | Sep 28, 2016 | Issued |