
Lissi Mojica Marquis
Examiner (ID: 14253)
| Most Active Art Unit | 3104 |
| Art Unit(s) | 3613, 3107, 3614, 3661, 3104, 3105 |
| Total Applications | 667 |
| Issued Applications | 565 |
| Pending Applications | 34 |
| Abandoned Applications | 68 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17318858
[patent_doc_number] => 20210407908
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-30
[patent_title] => MEMORY DEVICE WITH AIR GAPS FOR REDUCING CAPACITIVE COUPLING
[patent_app_type] => utility
[patent_app_number] => 16/912093
[patent_app_country] => US
[patent_app_date] => 2020-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7805
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16912093
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/912093 | Memory device with air gaps for reducing capacitive coupling | Jun 24, 2020 | Issued |
Array
(
[id] => 16752434
[patent_doc_number] => 20210104446
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-04-08
[patent_title] => PACKAGED SEMICONDUCTOR DEVICES HAVING ENHANCED THERMAL TRANSPORT AND METHODS OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/908128
[patent_app_country] => US
[patent_app_date] => 2020-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7222
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16908128
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/908128 | Packaged semiconductor devices having enhanced thermal transport and methods of manufacturing the same | Jun 21, 2020 | Issued |
Array
(
[id] => 17365965
[patent_doc_number] => 11232996
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-01-25
[patent_title] => Semiconductor device package comprising thermal interface layer and method of fabricating of the same
[patent_app_type] => utility
[patent_app_number] => 16/904685
[patent_app_country] => US
[patent_app_date] => 2020-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 26
[patent_no_of_words] => 9801
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16904685
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/904685 | Semiconductor device package comprising thermal interface layer and method of fabricating of the same | Jun 17, 2020 | Issued |
Array
(
[id] => 17295396
[patent_doc_number] => 20210391235
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-16
[patent_title] => LIDDED MICROELECTRONIC DEVICE PACKAGES AND RELATED SYSTEMS, APPARATUS, AND METHODS OF MANUFACTURE
[patent_app_type] => utility
[patent_app_number] => 16/902390
[patent_app_country] => US
[patent_app_date] => 2020-06-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11508
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 43
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16902390
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/902390 | Lidded microelectronic device packages and related systems, apparatus, and methods of manufacture | Jun 15, 2020 | Issued |
Array
(
[id] => 16331868
[patent_doc_number] => 20200302834
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-09-24
[patent_title] => ORGANIC EL DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/895066
[patent_app_country] => US
[patent_app_date] => 2020-06-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8291
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16895066
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/895066 | Organic el display device | Jun 7, 2020 | Issued |
Array
(
[id] => 17638144
[patent_doc_number] => 11348878
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-05-31
[patent_title] => Reinforced semiconductor die and related methods
[patent_app_type] => utility
[patent_app_number] => 16/886395
[patent_app_country] => US
[patent_app_date] => 2020-05-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 3636
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16886395
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/886395 | Reinforced semiconductor die and related methods | May 27, 2020 | Issued |
Array
(
[id] => 16951715
[patent_doc_number] => 20210210407
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-07-08
[patent_title] => POWER MODULE
[patent_app_type] => utility
[patent_app_number] => 16/884403
[patent_app_country] => US
[patent_app_date] => 2020-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4358
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16884403
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/884403 | Power module | May 26, 2020 | Issued |
Array
(
[id] => 17262795
[patent_doc_number] => 20210375780
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-02
[patent_title] => PATTERNING A TRANSPARENT WAFER TO FORM AN ALIGNMENT MARK IN THE TRANSPARENT WAFER
[patent_app_type] => utility
[patent_app_number] => 16/884437
[patent_app_country] => US
[patent_app_date] => 2020-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11966
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16884437
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/884437 | Patterning a transparent wafer to form an alignment mark in the transparent wafer | May 26, 2020 | Issued |
Array
(
[id] => 17516836
[patent_doc_number] => 11295997
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-04-05
[patent_title] => Semiconductor device manufacturing method and semiconductor device
[patent_app_type] => utility
[patent_app_number] => 16/884037
[patent_app_country] => US
[patent_app_date] => 2020-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 22
[patent_no_of_words] => 6547
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16884037
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/884037 | Semiconductor device manufacturing method and semiconductor device | May 25, 2020 | Issued |
Array
(
[id] => 18073887
[patent_doc_number] => 11532729
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-12-20
[patent_title] => Method for non-resist nanolithography
[patent_app_type] => utility
[patent_app_number] => 16/883195
[patent_app_country] => US
[patent_app_date] => 2020-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 16
[patent_no_of_words] => 6694
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16883195
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/883195 | Method for non-resist nanolithography | May 25, 2020 | Issued |
Array
(
[id] => 18766956
[patent_doc_number] => 11817365
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-11-14
[patent_title] => Thermal mitigation die using back side etch
[patent_app_type] => utility
[patent_app_number] => 16/883812
[patent_app_country] => US
[patent_app_date] => 2020-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 4182
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16883812
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/883812 | Thermal mitigation die using back side etch | May 25, 2020 | Issued |
Array
(
[id] => 16301113
[patent_doc_number] => 20200286836
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-09-10
[patent_title] => COBALT BASED INTERCONNECTS AND METHODS OF FABRICATION THEREOF
[patent_app_type] => utility
[patent_app_number] => 16/881530
[patent_app_country] => US
[patent_app_date] => 2020-05-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9575
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16881530
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/881530 | Cobalt based interconnects and methods of fabrication thereof | May 21, 2020 | Issued |
Array
(
[id] => 16920413
[patent_doc_number] => 20210193505
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-06-24
[patent_title] => DIELECTRIC CAPPING STRUCTURE OVERLYING A CONDUCTIVE STRUCTURE TO INCREASE STABILITY
[patent_app_type] => utility
[patent_app_number] => 16/876432
[patent_app_country] => US
[patent_app_date] => 2020-05-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9127
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16876432
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/876432 | Dielectric capping structure overlying a conductive structure to increase stability | May 17, 2020 | Issued |
Array
(
[id] => 18032003
[patent_doc_number] => 11515201
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-11-29
[patent_title] => Integrated circuit device including air gaps and method of manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 16/872955
[patent_app_country] => US
[patent_app_date] => 2020-05-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 8221
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16872955
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/872955 | Integrated circuit device including air gaps and method of manufacturing the same | May 11, 2020 | Issued |
Array
(
[id] => 16253325
[patent_doc_number] => 20200262699
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-08-20
[patent_title] => MICRO-ELECTRO-MECHANICAL DEVICE HAVING TWO BURIED CAVITIES AND MANUFACTURING PROCESS THEREOF
[patent_app_type] => utility
[patent_app_number] => 16/869159
[patent_app_country] => US
[patent_app_date] => 2020-05-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6960
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16869159
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/869159 | Micro-electro-mechanical device having two buried cavities and manufacturing process thereof | May 6, 2020 | Issued |
Array
(
[id] => 16715662
[patent_doc_number] => 20210082809
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-18
[patent_title] => SEMICONDUCTOR DEVICES
[patent_app_type] => utility
[patent_app_number] => 16/865544
[patent_app_country] => US
[patent_app_date] => 2020-05-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9475
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16865544
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/865544 | Semiconductor devices having vias on a scribe lane region | May 3, 2020 | Issued |
Array
(
[id] => 16241545
[patent_doc_number] => 20200258779
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-08-13
[patent_title] => FIELD EFFECT TRANSISTOR DEVICES WITH SELF-ALIGNED SOURCE/DRAIN CONTACTS AND GATE CONTACTS POSITIONED OVER ACTIVE TRANSISTORS
[patent_app_type] => utility
[patent_app_number] => 16/860835
[patent_app_country] => US
[patent_app_date] => 2020-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7800
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16860835
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/860835 | Field effect transistor devices with self-aligned source/drain contacts and gate contacts positioned over active transistors | Apr 27, 2020 | Issued |
Array
(
[id] => 20186961
[patent_doc_number] => 12398066
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-08-26
[patent_title] => Method for producing a display having a carrier substrate, a carrier substrate produced according to said method, and a cover glass intended for a flexible display
[patent_app_type] => utility
[patent_app_number] => 17/610733
[patent_app_country] => US
[patent_app_date] => 2020-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 0
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17610733
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/610733 | Method for producing a display having a carrier substrate, a carrier substrate produced according to said method, and a cover glass intended for a flexible display | Apr 26, 2020 | Issued |
Array
(
[id] => 17652695
[patent_doc_number] => 11355435
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-06-07
[patent_title] => Semiconductor device with air gaps
[patent_app_type] => utility
[patent_app_number] => 16/857931
[patent_app_country] => US
[patent_app_date] => 2020-04-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 40
[patent_figures_cnt] => 40
[patent_no_of_words] => 8918
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 232
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16857931
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/857931 | Semiconductor device with air gaps | Apr 23, 2020 | Issued |
Array
(
[id] => 17551521
[patent_doc_number] => 20220122863
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-21
[patent_title] => TRANSFER DEVICE AND TRANSFER METHOD FOR MICRO LIGHT-EMITTING DIODE (MICRO LED), AND DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/767135
[patent_app_country] => US
[patent_app_date] => 2020-04-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4935
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16767135
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/767135 | Transfer device and transfer method for micro light-emitting diode (micro LED), and display device | Apr 21, 2020 | Issued |