Search

Lissi Mojica Marquis

Examiner (ID: 14253)

Most Active Art Unit
3104
Art Unit(s)
3613, 3107, 3614, 3661, 3104, 3105
Total Applications
667
Issued Applications
565
Pending Applications
34
Abandoned Applications
68

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13293231 [patent_doc_number] => 10157816 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-18 [patent_title] => Phase changing on-chip thermal heat sink [patent_app_type] => utility [patent_app_number] => 15/899791 [patent_app_country] => US [patent_app_date] => 2018-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 20 [patent_no_of_words] => 5926 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15899791 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/899791
Phase changing on-chip thermal heat sink Feb 19, 2018 Issued
Array ( [id] => 13306835 [patent_doc_number] => 20180204954 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-19 [patent_title] => TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/866309 [patent_app_country] => US [patent_app_date] => 2018-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7752 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15866309 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/866309
Transistor array panel and manufacturing method thereof Jan 8, 2018 Issued
Array ( [id] => 12917941 [patent_doc_number] => 20180197823 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-12 [patent_title] => SEMICONDUCTOR DEVICE CHIP AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE CHIP [patent_app_type] => utility [patent_app_number] => 15/865896 [patent_app_country] => US [patent_app_date] => 2018-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2820 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15865896 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/865896
Semiconductor device chip and method of manufacturing semiconductor device chip Jan 8, 2018 Issued
Array ( [id] => 16773891 [patent_doc_number] => 10985011 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-20 [patent_title] => Structure and formation method of semiconductor device with resistive elements [patent_app_type] => utility [patent_app_number] => 15/866022 [patent_app_country] => US [patent_app_date] => 2018-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 27 [patent_no_of_words] => 6268 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15866022 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/866022
Structure and formation method of semiconductor device with resistive elements Jan 8, 2018 Issued
Array ( [id] => 14573751 [patent_doc_number] => 20190214483 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-11 [patent_title] => VFET Bottom Epitaxy Formed with Anchors [patent_app_type] => utility [patent_app_number] => 15/865902 [patent_app_country] => US [patent_app_date] => 2018-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8556 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15865902 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/865902
VFET bottom epitaxy formed with anchors Jan 8, 2018 Issued
Array ( [id] => 15792219 [patent_doc_number] => 10629842 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-21 [patent_title] => Display device and method of fabricating the same [patent_app_type] => utility [patent_app_number] => 15/866320 [patent_app_country] => US [patent_app_date] => 2018-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 8735 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15866320 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/866320
Display device and method of fabricating the same Jan 8, 2018 Issued
Array ( [id] => 14566523 [patent_doc_number] => 20190210868 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-11 [patent_title] => MICRO-ELECTRO-MECHANICAL DEVICE HAVING TWO BURIED CAVITIES AND MANUFACTURING PROCESS THEREOF [patent_app_type] => utility [patent_app_number] => 15/866380 [patent_app_country] => US [patent_app_date] => 2018-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6960 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15866380 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/866380
Micro-electro-mechanical device having two buried cavities and manufacturing process thereof Jan 8, 2018 Issued
Array ( [id] => 12706303 [patent_doc_number] => 20180127267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-10 [patent_title] => MEMS SENSOR PACKAGE SYSTEMS AND METHODS [patent_app_type] => utility [patent_app_number] => 15/864787 [patent_app_country] => US [patent_app_date] => 2018-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3907 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15864787 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/864787
MEMS sensor package systems and methods Jan 7, 2018 Issued
Array ( [id] => 12738985 [patent_doc_number] => 20180138162 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-17 [patent_title] => DISPLAY APPARATUS AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/851718 [patent_app_country] => US [patent_app_date] => 2017-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8644 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15851718 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/851718
Display apparatus and manufacturing method thereof Dec 20, 2017 Issued
Array ( [id] => 14151417 [patent_doc_number] => 10256097 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-09 [patent_title] => Forming a metal contact layer on silicon carbide and semiconductor device with metal contact structure [patent_app_type] => utility [patent_app_number] => 15/846591 [patent_app_country] => US [patent_app_date] => 2017-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 32 [patent_no_of_words] => 10035 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15846591 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/846591
Forming a metal contact layer on silicon carbide and semiconductor device with metal contact structure Dec 18, 2017 Issued
Array ( [id] => 12897298 [patent_doc_number] => 20180190941 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => ELECTROLUMINESCENT DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 15/847725 [patent_app_country] => US [patent_app_date] => 2017-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6146 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15847725 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/847725
Electroluminescent display device Dec 18, 2017 Issued
Array ( [id] => 12873223 [patent_doc_number] => 20180182916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-28 [patent_title] => GROUP III NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE AND PRODUCTION METHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 15/847648 [patent_app_country] => US [patent_app_date] => 2017-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5146 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15847648 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/847648
GROUP III NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE AND PRODUCTION METHOD THEREFOR Dec 18, 2017 Abandoned
Array ( [id] => 17196060 [patent_doc_number] => 11164827 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-02 [patent_title] => Substrate with gradiated dielectric for reducing impedance mismatch [patent_app_type] => utility [patent_app_number] => 16/473962 [patent_app_country] => US [patent_app_date] => 2017-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 12094 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16473962 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/473962
Substrate with gradiated dielectric for reducing impedance mismatch Dec 18, 2017 Issued
Array ( [id] => 12848953 [patent_doc_number] => 20180174824 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-21 [patent_title] => PROCESS OF FORMING EPITAXIAL SUBSTRATE AND SEMICONDUCTOR DEVICE PROVIDED ON THE SAME [patent_app_type] => utility [patent_app_number] => 15/847171 [patent_app_country] => US [patent_app_date] => 2017-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4551 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15847171 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/847171
Process of forming epitaxial substrate and semiconductor device provided on the same Dec 18, 2017 Issued
Array ( [id] => 14476375 [patent_doc_number] => 20190189836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => VERTICAL TYPE LIGHT EMITTING DIODE DIE AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 15/844785 [patent_app_country] => US [patent_app_date] => 2017-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3804 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15844785 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/844785
Vertical type light emitting diode die and method for fabricating the same Dec 17, 2017 Issued
Array ( [id] => 17107664 [patent_doc_number] => 11127892 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-21 [patent_title] => Reducing parasitic capacitance and coupling to inductive coupler modes [patent_app_type] => utility [patent_app_number] => 16/473779 [patent_app_country] => US [patent_app_date] => 2017-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 8277 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16473779 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/473779
Reducing parasitic capacitance and coupling to inductive coupler modes Dec 14, 2017 Issued
Array ( [id] => 14459715 [patent_doc_number] => 10325830 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-06-18 [patent_title] => Multipart lid for a semiconductor package with multiple components [patent_app_type] => utility [patent_app_number] => 15/826856 [patent_app_country] => US [patent_app_date] => 2017-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 6940 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15826856 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/826856
Multipart lid for a semiconductor package with multiple components Nov 29, 2017 Issued
Array ( [id] => 13071413 [patent_doc_number] => 10056495 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-21 [patent_title] => Thin film transistor and display device using the same [patent_app_type] => utility [patent_app_number] => 15/826820 [patent_app_country] => US [patent_app_date] => 2017-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 5100 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15826820 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/826820
Thin film transistor and display device using the same Nov 29, 2017 Issued
Array ( [id] => 15170335 [patent_doc_number] => 10490674 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-26 [patent_title] => Semiconductor device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 15/821349 [patent_app_country] => US [patent_app_date] => 2017-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3640 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15821349 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/821349
Semiconductor device and manufacturing method thereof Nov 21, 2017 Issued
Array ( [id] => 13976787 [patent_doc_number] => 10217761 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-02-26 [patent_title] => Semiconductor structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 15/821344 [patent_app_country] => US [patent_app_date] => 2017-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2938 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15821344 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/821344
Semiconductor structure and manufacturing method thereof Nov 21, 2017 Issued
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