Long D Pham

Array ( [id] => 12739603 [patent_doc_number] => 20180138368 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-17 [patent_title] => LIGHT EMITTING DIODE HAVING SIDE REFLECTION LAYER [patent_app_type] => utility [patent_app_number] => 15/811900 [patent_app_country] => US [patent_app_date] => 2017-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13878 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15811900 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13976661 [patent_doc_number] => 10217696 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-26 [patent_title] => Non-bridging contact via structures in proximity [patent_app_type] => utility [patent_app_number] => 15/811198 [patent_app_country] => US [patent_app_date] => 2017-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 48 [patent_no_of_words] => 6525 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15811198 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14317589 [patent_doc_number] => 20190148498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-16 [patent_title] => Passivation Structure For GaN Field Effect Transistor [patent_app_type] => utility [patent_app_number] => 15/810927 [patent_app_country] => US [patent_app_date] => 2017-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7972 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15810927 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16173020 [patent_doc_number] => 10714600 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-14 [patent_title] => Bipolar junction transistor (BJT) base conductor pullback [patent_app_type] => utility [patent_app_number] => 15/793073 [patent_app_country] => US [patent_app_date] => 2017-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 6262 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15793073 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17941705 [patent_doc_number] => 11476164 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-18 [patent_title] => Integrated circuit structures having differentiated workfunction layers [patent_app_type] => utility [patent_app_number] => 16/631352 [patent_app_country] => US [patent_app_date] => 2017-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 9171 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16631352 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12223356 [patent_doc_number] => 20180061716 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-01 [patent_title] => 'SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/680406 [patent_app_country] => US [patent_app_date] => 2017-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6112 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15680406 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15889869 [patent_doc_number] => 10651291 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-12 [patent_title] => Inner spacer formation in a nanosheet field-effect transistor [patent_app_type] => utility [patent_app_number] => 15/680467 [patent_app_country] => US [patent_app_date] => 2017-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 5315 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15680467 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12223470 [patent_doc_number] => 20180061830 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-01 [patent_title] => 'SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/679362 [patent_app_country] => US [patent_app_date] => 2017-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6302 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15679362 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13878703 [patent_doc_number] => 20190035692 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-31 [patent_title] => METHODS OF FORMING CONDUCTIVE SPACERS FOR GATE CONTACTS AND THE RESULTING DEVICE [patent_app_type] => utility [patent_app_number] => 15/658524 [patent_app_country] => US [patent_app_date] => 2017-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4681 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15658524 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12516495 [patent_doc_number] => 10002966 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-06-19 [patent_title] => Field effect transistor and device thereof [patent_app_type] => utility [patent_app_number] => 15/655919 [patent_app_country] => US [patent_app_date] => 2017-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2207 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15655919 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13847977 [patent_doc_number] => 20190027473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-24 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 15/652719 [patent_app_country] => US [patent_app_date] => 2017-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13551 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15652719 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13847971 [patent_doc_number] => 20190027470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-24 [patent_title] => Step Fin Field-Effect-Transistor (FinFET) with Slim Top of Fin and Thick Bottom of Fin for Electro-Static-Discharge (ESD) or Electrical Over-Stress (EOS) Protection [patent_app_type] => utility [patent_app_number] => 15/652645 [patent_app_country] => US [patent_app_date] => 2017-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6339 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15652645 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13132091 [patent_doc_number] => 10083985 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-25 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 15/651818 [patent_app_country] => US [patent_app_date] => 2017-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 5926 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 305 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15651818 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16280408 [patent_doc_number] => 10763451 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-01 [patent_title] => Display device [patent_app_type] => utility [patent_app_number] => 15/649701 [patent_app_country] => US [patent_app_date] => 2017-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 17945 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15649701 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12236230 [patent_doc_number] => 20180069093 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-08 [patent_title] => 'SEMICONDUCTOR DEVICE LAYOUT STRUCTURE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/649422 [patent_app_country] => US [patent_app_date] => 2017-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6356 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15649422 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15015221 [patent_doc_number] => 10453769 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-22 [patent_title] => Thermal management structure with integrated heat sink [patent_app_type] => utility [patent_app_number] => 15/645321 [patent_app_country] => US [patent_app_date] => 2017-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4950 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15645321 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15077603 [patent_doc_number] => 10468300 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-05 [patent_title] => Contacting source and drain of a transistor device [patent_app_type] => utility [patent_app_number] => 15/641927 [patent_app_country] => US [patent_app_date] => 2017-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 5317 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15641927 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13740751 [patent_doc_number] => 20180374845 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-27 [patent_title] => METHOD FOR MANUFACTURING MONOLITHIC THREE-DIMENSIONAL (3D) INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 15/633016 [patent_app_country] => US [patent_app_date] => 2017-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11178 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15633016 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13724379 [patent_doc_number] => 20170373145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-28 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/631257 [patent_app_country] => US [patent_app_date] => 2017-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19015 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15631257 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15015183 [patent_doc_number] => 10453750 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-22 [patent_title] => Stacked elongated nanoshapes of different semiconductor materials and structures that incorporate the nanoshapes [patent_app_type] => utility [patent_app_number] => 15/629884 [patent_app_country] => US [patent_app_date] => 2017-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 25 [patent_no_of_words] => 8959 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15629884 [rel_patent_id] =>[rel_patent_doc_number] =>)