Long Huynh Le

Array ( [id] => 11883774 [patent_doc_number] => 09754955 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-05 [patent_title] => 'High-K-last manufacturing process for embedded memory with metal-oxide-nitride-oxide-silicon (MONOS) memory cells' [patent_app_type] => utility [patent_app_number] => 14/983682 [patent_app_country] => US [patent_app_date] => 2015-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 27 [patent_no_of_words] => 8604 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14983682 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11732770 [patent_doc_number] => 20170194213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-06 [patent_title] => 'Multi-Gate Device and Method of Fabrication Thereof' [patent_app_type] => utility [patent_app_number] => 14/983816 [patent_app_country] => US [patent_app_date] => 2015-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 10918 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14983816 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12089116 [patent_doc_number] => 09842850 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-12 [patent_title] => 'High-K-last manufacturing process for embedded memory with silicon-oxide-nitride-oxide-silicon (SONOS) memory cells' [patent_app_type] => utility [patent_app_number] => 14/983686 [patent_app_country] => US [patent_app_date] => 2015-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 23 [patent_no_of_words] => 7283 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14983686 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11694350 [patent_doc_number] => 20170170068 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-15 [patent_title] => 'SELF-ALIGNED LOW DIELECTRIC CONSTANT GATE CAP AND A METHOD OF FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/970120 [patent_app_country] => US [patent_app_date] => 2015-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3772 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14970120 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13159721 [patent_doc_number] => 10096596 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-09 [patent_title] => Semiconductor device structure having a plurality of gate structures [patent_app_type] => utility [patent_app_number] => 14/970036 [patent_app_country] => US [patent_app_date] => 2015-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 6901 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14970036 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12089249 [patent_doc_number] => 09842986 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-12 [patent_title] => 'Semiconductor structure and method of forming the same' [patent_app_type] => utility [patent_app_number] => 14/969697 [patent_app_country] => US [patent_app_date] => 2015-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6685 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14969697 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12214795 [patent_doc_number] => 09911610 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-06 [patent_title] => 'Semiconductor device having a metal-semiconductor junction and manufacturing therefor' [patent_app_type] => utility [patent_app_number] => 14/969663 [patent_app_country] => US [patent_app_date] => 2015-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 6575 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14969663 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13099249 [patent_doc_number] => 10068971 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-04 [patent_title] => Junctionless field-effect transistor having ultra-thin low-crystalline-silicon channel and fabrication method thereof [patent_app_type] => utility [patent_app_number] => 14/969172 [patent_app_country] => US [patent_app_date] => 2015-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 3369 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14969172 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11694498 [patent_doc_number] => 20170170215 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-15 [patent_title] => 'SEMICONDUCTOR DEVICE STRUCTURE WITH ANTI-ACID LAYER AND METHOD FOR FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/970022 [patent_app_country] => US [patent_app_date] => 2015-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5747 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14970022 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11690722 [patent_doc_number] => 20170166438 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-15 [patent_title] => 'SMALL WAFER AREA MEMS SWITCH' [patent_app_type] => utility [patent_app_number] => 14/969329 [patent_app_country] => US [patent_app_date] => 2015-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11399 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14969329 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12109167 [patent_doc_number] => 09865655 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-09 [patent_title] => 'Memory cell structure with resistance-change material and method for forming the same' [patent_app_type] => utility [patent_app_number] => 14/970001 [patent_app_country] => US [patent_app_date] => 2015-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 6781 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14970001 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10826413 [patent_doc_number] => 20160172581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'SPIN TORQUE MAJORITY GATE DEVICE' [patent_app_type] => utility [patent_app_number] => 14/970215 [patent_app_country] => US [patent_app_date] => 2015-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5326 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14970215 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10753174 [patent_doc_number] => 20160099326 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-07 [patent_title] => 'METHOD FOR MAKING AN INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/965519 [patent_app_country] => US [patent_app_date] => 2015-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 9859 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14965519 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11890900 [patent_doc_number] => 09761465 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-12 [patent_title] => 'Systems and methods for mechanical and electrical package substrate issue mitigation' [patent_app_type] => utility [patent_app_number] => 14/961230 [patent_app_country] => US [patent_app_date] => 2015-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3653 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14961230 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12147637 [patent_doc_number] => 09881897 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-30 [patent_title] => 'Manufacturing method of ultra-thin semiconductor device package assembly' [patent_app_type] => utility [patent_app_number] => 14/954981 [patent_app_country] => US [patent_app_date] => 2015-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 5618 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 394 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14954981 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10826085 [patent_doc_number] => 20160172253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'ELECTRIC-PROGRAMMABLE MAGNETIC MODULE AND PICKING-UP AND PLACEMENT PROCESS FOR ELECTRONIC DEVICES' [patent_app_type] => utility [patent_app_number] => 14/954993 [patent_app_country] => US [patent_app_date] => 2015-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 4542 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14954993 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12027050 [patent_doc_number] => 20170317148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-02 [patent_title] => 'ORGANIC ELECTROLUMINESCENCE DEVICE, ILLUMINATION DEVICE, AND DISPLAY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/529519 [patent_app_country] => US [patent_app_date] => 2015-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 13456 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15529519 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13598321 [patent_doc_number] => 20180350709 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-06 [patent_title] => ELECTRONIC PACKAGE THAT INCLUDES LAMINATION LAYER [patent_app_type] => utility [patent_app_number] => 15/778042 [patent_app_country] => US [patent_app_date] => 2015-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4129 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15778042 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11653499 [patent_doc_number] => 20170149404 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-25 [patent_title] => 'ON-CHIP ELECTROMAGNETIC BANDGAP (EBG) STRUCTURE FOR NOISE SUPPRESSION' [patent_app_type] => utility [patent_app_number] => 14/948477 [patent_app_country] => US [patent_app_date] => 2015-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10597 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14948477 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15109401 [patent_doc_number] => 10476033 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-12 [patent_title] => Light-emitting element, display panel, display device, electronic device and method for producing light-emitting element [patent_app_type] => utility [patent_app_number] => 15/529981 [patent_app_country] => US [patent_app_date] => 2015-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 67 [patent_no_of_words] => 39941 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15529981 [rel_patent_id] =>[rel_patent_doc_number] =>)