
Long K. Tran
Examiner (ID: 16014)
| Most Active Art Unit | 2818 |
| Art Unit(s) | 2818, 2829 |
| Total Applications | 1616 |
| Issued Applications | 1396 |
| Pending Applications | 78 |
| Abandoned Applications | 146 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
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[patent_doc_number] => 20140057369
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-02-27
[patent_title] => 'METHODS FOR FORMING INTERCONNECTION LINE USING SCREEN PRINTING TECHNIQUE'
[patent_app_type] => utility
[patent_app_number] => 13/719082
[patent_app_country] => US
[patent_app_date] => 2012-12-18
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/719082 | Methods for forming interconnection line using screen printing technique | Dec 17, 2012 | Issued |
Array
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[patent_kind] => B2
[patent_issue_date] => 2015-10-13
[patent_title] => 'System and method for matching electrode resistances in OLED light panels'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/713072 | System and method for matching electrode resistances in OLED light panels | Dec 12, 2012 | Issued |
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[patent_issue_date] => 2014-06-19
[patent_title] => 'SEMICONDUCTOR DIODE ASSEMBLY'
[patent_app_type] => utility
[patent_app_number] => 13/713243
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Array
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[patent_doc_number] => 20140167119
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[patent_kind] => A1
[patent_issue_date] => 2014-06-19
[patent_title] => 'METHODS OF FORMING A SIDEWALL SPACER HAVING A GENERALLY TRIANGULAR SHAPE AND A SEMICONDUCTOR DEVICE HAVING SUCH A SPACER'
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Array
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Array
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[patent_doc_number] => 20140167212
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[patent_issue_date] => 2014-06-19
[patent_title] => 'Termination Structure with Multiple Embedded Potential Spreading Capacitive Structures for Trench MOSFET and Method'
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[patent_app_number] => 13/712980
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Array
(
[id] => 9536195
[patent_doc_number] => 20140160841
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[patent_issue_date] => 2014-06-12
[patent_title] => 'SELF-ALIGNED FLOATING GATE IN A VERTICAL MEMORY STRUCTURE'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/711974 | Self-aligned floating gate in a vertical memory structure | Dec 11, 2012 | Issued |
Array
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[patent_issue_date] => 2014-07-15
[patent_title] => 'Display substrate and method of fabricating the same'
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Array
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[patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME'
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Array
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[patent_title] => 'Thin Film Transistor, Array Substrate And Method For Manufacturing The Same, Display Device'
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Array
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Array
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