
Long Pham
Examiner (ID: 5269, Phone: (571)272-1714 , Office: P/2814 )
| Most Active Art Unit | 2814 |
| Art Unit(s) | 2822, 2899, 2897, 2823, 1107, 2814, 2812, 1763 |
| Total Applications | 3774 |
| Issued Applications | 3306 |
| Pending Applications | 160 |
| Abandoned Applications | 335 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5019498
[patent_doc_number] => 20070145464
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-06-28
[patent_title] => 'Random access memory device utilizing a vertically oriented select transistor'
[patent_app_type] => utility
[patent_app_number] => 11/708616
[patent_app_country] => US
[patent_app_date] => 2007-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5378
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0145/20070145464.pdf
[firstpage_image] =>[orig_patent_app_number] => 11708616
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/708616 | Random access memory device utilizing a vertically oriented select transistor | Feb 20, 2007 | Issued |
Array
(
[id] => 330402
[patent_doc_number] => 07510897
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-03-31
[patent_title] => 'Photodiode with self-aligned implants for high quantum efficiency and method of formation'
[patent_app_type] => utility
[patent_app_number] => 11/708067
[patent_app_country] => US
[patent_app_date] => 2007-02-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 14
[patent_no_of_words] => 5465
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/510/07510897.pdf
[firstpage_image] =>[orig_patent_app_number] => 11708067
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/708067 | Photodiode with self-aligned implants for high quantum efficiency and method of formation | Feb 19, 2007 | Issued |
Array
(
[id] => 4902738
[patent_doc_number] => 20080112151
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-05-15
[patent_title] => 'Overmolded electronic module with an integrated electromagnetic shield using SMT shield wall components'
[patent_app_type] => utility
[patent_app_number] => 11/708382
[patent_app_country] => US
[patent_app_date] => 2007-02-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3738
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0112/20080112151.pdf
[firstpage_image] =>[orig_patent_app_number] => 11708382
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/708382 | Overmolded electronic module with an integrated electromagnetic shield using SMT shield wall components | Feb 18, 2007 | Abandoned |
Array
(
[id] => 278322
[patent_doc_number] => 07557399
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-07-07
[patent_title] => 'Metal-insulator-metal capacitors'
[patent_app_type] => utility
[patent_app_number] => 11/704088
[patent_app_country] => US
[patent_app_date] => 2007-02-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 17
[patent_no_of_words] => 4441
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/557/07557399.pdf
[firstpage_image] =>[orig_patent_app_number] => 11704088
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/704088 | Metal-insulator-metal capacitors | Feb 7, 2007 | Issued |
Array
(
[id] => 585075
[patent_doc_number] => 07442611
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-10-28
[patent_title] => 'Method of applying stresses to PFET and NFET transistor channels for improved performance'
[patent_app_type] => utility
[patent_app_number] => 11/657154
[patent_app_country] => US
[patent_app_date] => 2007-01-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 11
[patent_no_of_words] => 3670
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 239
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/442/07442611.pdf
[firstpage_image] =>[orig_patent_app_number] => 11657154
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/657154 | Method of applying stresses to PFET and NFET transistor channels for improved performance | Jan 23, 2007 | Issued |
Array
(
[id] => 5014108
[patent_doc_number] => 20070257316
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-11-08
[patent_title] => 'Semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/655202
[patent_app_country] => US
[patent_app_date] => 2007-01-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 3876
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0257/20070257316.pdf
[firstpage_image] =>[orig_patent_app_number] => 11655202
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/655202 | Semiconductor device | Jan 18, 2007 | Abandoned |
Array
(
[id] => 4762768
[patent_doc_number] => 20080173977
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-24
[patent_title] => 'POST STI TRENCH CAPACITOR'
[patent_app_type] => utility
[patent_app_number] => 11/624385
[patent_app_country] => US
[patent_app_date] => 2007-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 2984
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0173/20080173977.pdf
[firstpage_image] =>[orig_patent_app_number] => 11624385
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/624385 | Post STI trench capacitor | Jan 17, 2007 | Issued |
Array
(
[id] => 836960
[patent_doc_number] => 07393775
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-07-01
[patent_title] => 'Semiconductor integrated circuit device having diagonal direction wiring and layout method therefor'
[patent_app_type] => utility
[patent_app_number] => 11/653261
[patent_app_country] => US
[patent_app_date] => 2007-01-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 31
[patent_no_of_words] => 7372
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/393/07393775.pdf
[firstpage_image] =>[orig_patent_app_number] => 11653261
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/653261 | Semiconductor integrated circuit device having diagonal direction wiring and layout method therefor | Jan 15, 2007 | Issued |
Array
(
[id] => 141770
[patent_doc_number] => 07687396
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-03-30
[patent_title] => 'Method of forming silicided gates using buried metal layers'
[patent_app_type] => utility
[patent_app_number] => 11/617897
[patent_app_country] => US
[patent_app_date] => 2006-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 12
[patent_no_of_words] => 3105
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/687/07687396.pdf
[firstpage_image] =>[orig_patent_app_number] => 11617897
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/617897 | Method of forming silicided gates using buried metal layers | Dec 28, 2006 | Issued |
Array
(
[id] => 8364178
[patent_doc_number] => 08253246
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-08-28
[patent_title] => 'Wiring structure and electronic device designed on basis of electron wave-particle duality'
[patent_app_type] => utility
[patent_app_number] => 12/087155
[patent_app_country] => US
[patent_app_date] => 2006-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 16
[patent_no_of_words] => 14300
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12087155
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/087155 | Wiring structure and electronic device designed on basis of electron wave-particle duality | Dec 26, 2006 | Issued |
Array
(
[id] => 4639475
[patent_doc_number] => 08017502
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-09-13
[patent_title] => 'Wafer system with partial cuts'
[patent_app_type] => utility
[patent_app_number] => 11/615929
[patent_app_country] => US
[patent_app_date] => 2006-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 5086
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[patent_words_short_claim] => 76
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/017/08017502.pdf
[firstpage_image] =>[orig_patent_app_number] => 11615929
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/615929 | Wafer system with partial cuts | Dec 21, 2006 | Issued |
Array
(
[id] => 5031698
[patent_doc_number] => 20070096237
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-05-03
[patent_title] => 'DESIGN AND FABRICATION OF RUGGED FRED, POWER MOSFET OR IGBT'
[patent_app_type] => utility
[patent_app_number] => 11/614897
[patent_app_country] => US
[patent_app_date] => 2006-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_claims] => 27
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0096/20070096237.pdf
[firstpage_image] =>[orig_patent_app_number] => 11614897
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/614897 | Design and fabrication of rugged FRED, power MOSFET or IGBT | Dec 20, 2006 | Issued |
Array
(
[id] => 4982919
[patent_doc_number] => 20070087477
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-04-19
[patent_title] => 'SEMICONDUCTOR DEVICE HAVING A LOW-RESISTANCE BUS INTERCONNECT, METHOD OF MANUFACTURING SAME, AND DISPLAY APPARATUS EMPLOYING SAME'
[patent_app_type] => utility
[patent_app_number] => 11/610940
[patent_app_country] => US
[patent_app_date] => 2006-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 6697
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0087/20070087477.pdf
[firstpage_image] =>[orig_patent_app_number] => 11610940
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/610940 | Semiconductor device having a low-resistance bus interconnect, method of manufacturing same, and display apparatus employing same | Dec 13, 2006 | Issued |
Array
(
[id] => 5250598
[patent_doc_number] => 20070132054
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-06-14
[patent_title] => 'MEMORY CELL HAVING STRESSED LAYERS'
[patent_app_type] => utility
[patent_app_number] => 11/609851
[patent_app_country] => US
[patent_app_date] => 2006-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 6078
[patent_no_of_claims] => 14
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0132/20070132054.pdf
[firstpage_image] =>[orig_patent_app_number] => 11609851
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/609851 | Memory cell having stressed layers | Dec 11, 2006 | Issued |
Array
(
[id] => 82785
[patent_doc_number] => 07745858
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-06-29
[patent_title] => 'Photodiode with self-aligned implants for high quantum efficiency and method of formation'
[patent_app_type] => utility
[patent_app_number] => 11/636979
[patent_app_country] => US
[patent_app_date] => 2006-12-12
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/745/07745858.pdf
[firstpage_image] =>[orig_patent_app_number] => 11636979
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/636979 | Photodiode with self-aligned implants for high quantum efficiency and method of formation | Dec 11, 2006 | Issued |
Array
(
[id] => 4980520
[patent_doc_number] => 20070085076
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-04-19
[patent_title] => 'Organic electronic device and method for manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 11/633924
[patent_app_country] => US
[patent_app_date] => 2006-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0085/20070085076.pdf
[firstpage_image] =>[orig_patent_app_number] => 11633924
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/633924 | Organic electronic device and method for manufacturing the same | Dec 4, 2006 | Issued |
Array
(
[id] => 5209303
[patent_doc_number] => 20070247887
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-10-25
[patent_title] => 'Semiconductor device having non-volatile memory and method of fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 11/633948
[patent_app_country] => US
[patent_app_date] => 2006-12-05
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[pdf_file] => publications/A1/0247/20070247887.pdf
[firstpage_image] =>[orig_patent_app_number] => 11633948
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/633948 | Semiconductor device having non-volatile memory and method of fabricating the same | Dec 4, 2006 | Issued |
Array
(
[id] => 5233840
[patent_doc_number] => 20070125995
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-06-07
[patent_title] => 'Horizontal emitting, vertical emitting, beam shaped, distributed feedback (DFB) lasers fabricated by growth over a patterned substrate with multiple overgrowth'
[patent_app_type] => utility
[patent_app_number] => 11/633148
[patent_app_country] => US
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[pdf_file] => publications/A1/0125/20070125995.pdf
[firstpage_image] =>[orig_patent_app_number] => 11633148
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/633148 | Horizontal emitting, vertical emitting, beam shaped, distributed feedback (DFB) lasers fabricated by growth over a patterned substrate with multiple overgrowth | Dec 3, 2006 | Issued |
Array
(
[id] => 5004738
[patent_doc_number] => 20070202307
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-08-30
[patent_title] => 'RIGID FLEXIBLE PRINTED CIRCUIT BOARD HAVING OPENINGS'
[patent_app_type] => utility
[patent_app_number] => 11/565869
[patent_app_country] => US
[patent_app_date] => 2006-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0202/20070202307.pdf
[firstpage_image] =>[orig_patent_app_number] => 11565869
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/565869 | RIGID FLEXIBLE PRINTED CIRCUIT BOARD HAVING OPENINGS | Nov 30, 2006 | Abandoned |
Array
(
[id] => 285391
[patent_doc_number] => 07550317
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-06-23
[patent_title] => 'Method for manufacture of wafer level package with air pads'
[patent_app_type] => utility
[patent_app_number] => 11/601808
[patent_app_country] => US
[patent_app_date] => 2006-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 20
[patent_no_of_words] => 3484
[patent_no_of_claims] => 16
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/550/07550317.pdf
[firstpage_image] =>[orig_patent_app_number] => 11601808
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/601808 | Method for manufacture of wafer level package with air pads | Nov 19, 2006 | Issued |