Search

Long Pham

Examiner (ID: 5269, Phone: (571)272-1714 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2822, 2899, 2897, 2823, 1107, 2814, 2812, 1763
Total Applications
3774
Issued Applications
3306
Pending Applications
160
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 928465 [patent_doc_number] => 07314775 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-01 [patent_title] => 'IT-CCD and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 11/500455 [patent_app_country] => US [patent_app_date] => 2006-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 23 [patent_no_of_words] => 4224 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/314/07314775.pdf [firstpage_image] =>[orig_patent_app_number] => 11500455 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/500455
IT-CCD and manufacturing method thereof Aug 7, 2006 Issued
Array ( [id] => 6240096 [patent_doc_number] => 20100133564 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-03 [patent_title] => 'Method for Producing Semiconductor Components and Thin-Film Semiconductor Component' [patent_app_type] => utility [patent_app_number] => 11/990099 [patent_app_country] => US [patent_app_date] => 2006-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5065 [patent_no_of_claims] => 78 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20100133564.pdf [firstpage_image] =>[orig_patent_app_number] => 11990099 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/990099
Method for producing semiconductor components and thin-film semiconductor component Aug 3, 2006 Issued
Array ( [id] => 8713830 [patent_doc_number] => 08399972 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-19 [patent_title] => 'Overmolded semiconductor package with a wirebond cage for EMI shielding' [patent_app_type] => utility [patent_app_number] => 11/499285 [patent_app_country] => US [patent_app_date] => 2006-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7297 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11499285 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/499285
Overmolded semiconductor package with a wirebond cage for EMI shielding Aug 3, 2006 Issued
Array ( [id] => 5608697 [patent_doc_number] => 20060270213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-30 [patent_title] => 'Organic electroluminescenst display panel and manufacturing method therefor' [patent_app_type] => utility [patent_app_number] => 11/498729 [patent_app_country] => US [patent_app_date] => 2006-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4749 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0270/20060270213.pdf [firstpage_image] =>[orig_patent_app_number] => 11498729 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/498729
Organic electroluminescenst display panel and manufacturing method therefor Aug 3, 2006 Abandoned
Array ( [id] => 5209331 [patent_doc_number] => 20070247915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-25 [patent_title] => 'Multiple time programmable (MTP) PMOS floating gate-based non-volatile memory device for a general-purpose CMOS technology with thick gate oxide' [patent_app_type] => utility [patent_app_number] => 11/498672 [patent_app_country] => US [patent_app_date] => 2006-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4951 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0247/20070247915.pdf [firstpage_image] =>[orig_patent_app_number] => 11498672 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/498672
Multiple time programmable (MTP) PMOS floating gate-based non-volatile memory device for a general-purpose CMOS technology with thick gate oxide Aug 1, 2006 Abandoned
Array ( [id] => 6457268 [patent_doc_number] => 20100090230 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-15 [patent_title] => 'CRYSTAL SILICON ELEMENT AND METHOD FOR FABRICATING SAME' [patent_app_type] => utility [patent_app_number] => 11/997399 [patent_app_country] => US [patent_app_date] => 2006-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 17812 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20100090230.pdf [firstpage_image] =>[orig_patent_app_number] => 11997399 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/997399
CRYSTAL SILICON ELEMENT AND METHOD FOR FABRICATING SAME Jul 31, 2006 Abandoned
Array ( [id] => 800595 [patent_doc_number] => 07425742 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-16 [patent_title] => 'NAND flash cell structure' [patent_app_type] => utility [patent_app_number] => 11/495245 [patent_app_country] => US [patent_app_date] => 2006-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 12118 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/425/07425742.pdf [firstpage_image] =>[orig_patent_app_number] => 11495245 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/495245
NAND flash cell structure Jul 27, 2006 Issued
Array ( [id] => 204564 [patent_doc_number] => 07629244 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-08 [patent_title] => 'Method of fabricating a single electron transistor having memory function' [patent_app_type] => utility [patent_app_number] => 11/491281 [patent_app_country] => US [patent_app_date] => 2006-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 9265 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/629/07629244.pdf [firstpage_image] =>[orig_patent_app_number] => 11491281 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/491281
Method of fabricating a single electron transistor having memory function Jul 23, 2006 Issued
Array ( [id] => 817428 [patent_doc_number] => 07411236 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-12 [patent_title] => 'Semiconductor storage device' [patent_app_type] => utility [patent_app_number] => 11/486104 [patent_app_country] => US [patent_app_date] => 2006-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 55 [patent_no_of_words] => 5002 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/411/07411236.pdf [firstpage_image] =>[orig_patent_app_number] => 11486104 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/486104
Semiconductor storage device Jul 13, 2006 Issued
Array ( [id] => 5661683 [patent_doc_number] => 20060252279 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-09 [patent_title] => 'Systems and methods for forming metal oxides using metal diketonates and/or ketoimines' [patent_app_type] => utility [patent_app_number] => 11/485770 [patent_app_country] => US [patent_app_date] => 2006-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 9044 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0252/20060252279.pdf [firstpage_image] =>[orig_patent_app_number] => 11485770 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/485770
Systems and methods for forming metal oxides using metal diketonates and/or ketoimines Jul 12, 2006 Issued
Array ( [id] => 5072934 [patent_doc_number] => 20070012909 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-18 [patent_title] => 'Semiconductor Device Including a Strained Superlattice Between at Least One Pair of Spaced Apart Stress Regions' [patent_app_type] => utility [patent_app_number] => 11/457269 [patent_app_country] => US [patent_app_date] => 2006-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7255 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20070012909.pdf [firstpage_image] =>[orig_patent_app_number] => 11457269 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/457269
Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions Jul 12, 2006 Issued
Array ( [id] => 4994695 [patent_doc_number] => 20070010040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-11 [patent_title] => 'Method for Making a Semiconductor Device Including a Strained Superlattice Layer Above a Stress Layer' [patent_app_type] => utility [patent_app_number] => 11/457263 [patent_app_country] => US [patent_app_date] => 2006-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7334 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20070010040.pdf [firstpage_image] =>[orig_patent_app_number] => 11457263 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/457263
Method for Making a Semiconductor Device Including a Strained Superlattice Layer Above a Stress Layer Jul 12, 2006 Abandoned
Array ( [id] => 5072935 [patent_doc_number] => 20070012910 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-18 [patent_title] => 'Semiconductor Device Including a Channel with a Non-Semiconductor Layer Monolayer' [patent_app_type] => utility [patent_app_number] => 11/457299 [patent_app_country] => US [patent_app_date] => 2006-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7166 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20070012910.pdf [firstpage_image] =>[orig_patent_app_number] => 11457299 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/457299
Semiconductor Device Including a Channel with a Non-Semiconductor Layer Monolayer Jul 12, 2006 Abandoned
Array ( [id] => 5075369 [patent_doc_number] => 20070015344 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-18 [patent_title] => 'Method for Making a Semiconductor Device Including a Strained Superlattice Between at Least One Pair of Spaced Apart Stress Regions' [patent_app_type] => utility [patent_app_number] => 11/457276 [patent_app_country] => US [patent_app_date] => 2006-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7281 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20070015344.pdf [firstpage_image] =>[orig_patent_app_number] => 11457276 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/457276
Method for Making a Semiconductor Device Including a Strained Superlattice Between at Least One Pair of Spaced Apart Stress Regions Jul 12, 2006 Abandoned
Array ( [id] => 5242338 [patent_doc_number] => 20070020833 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-25 [patent_title] => 'Method for Making a Semiconductor Device Including a Channel with a Non-Semiconductor Layer Monolayer' [patent_app_type] => utility [patent_app_number] => 11/457315 [patent_app_country] => US [patent_app_date] => 2006-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7168 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0020/20070020833.pdf [firstpage_image] =>[orig_patent_app_number] => 11457315 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/457315
Method for Making a Semiconductor Device Including a Channel with a Non-Semiconductor Layer Monolayer Jul 12, 2006 Abandoned
Array ( [id] => 5242365 [patent_doc_number] => 20070020860 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-25 [patent_title] => 'Method for Making Semiconductor Device Including a Strained Superlattice and Overlying Stress Layer and Related Methods' [patent_app_type] => utility [patent_app_number] => 11/457293 [patent_app_country] => US [patent_app_date] => 2006-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7241 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0020/20070020860.pdf [firstpage_image] =>[orig_patent_app_number] => 11457293 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/457293
Method for Making Semiconductor Device Including a Strained Superlattice and Overlying Stress Layer and Related Methods Jul 12, 2006 Abandoned
Array ( [id] => 5598705 [patent_doc_number] => 20060289049 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-28 [patent_title] => 'Semiconductor Device Having a Semiconductor-on-Insulator (SOI) Configuration and Including a Superlattice on a Thin Semiconductor Layer' [patent_app_type] => utility [patent_app_number] => 11/428015 [patent_app_country] => US [patent_app_date] => 2006-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5097 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0289/20060289049.pdf [firstpage_image] =>[orig_patent_app_number] => 11428015 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/428015
Semiconductor Device Having a Semiconductor-on-Insulator (SOI) Configuration and Including a Superlattice on a Thin Semiconductor Layer Jun 29, 2006 Abandoned
Array ( [id] => 6351902 [patent_doc_number] => 20100072472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-25 [patent_title] => 'Nanostructures With 0, 1, 2, and 3 Dimensions, With Negative Differential Resistance and Method for Making These Nanostructures' [patent_app_type] => utility [patent_app_number] => 11/922970 [patent_app_country] => US [patent_app_date] => 2006-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3983 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20100072472.pdf [firstpage_image] =>[orig_patent_app_number] => 11922970 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/922970
Nanostructures With 0, 1, 2, and 3 Dimensions, With Negative Differential Resistance and Method for Making These Nanostructures Jun 28, 2006 Abandoned
Array ( [id] => 6399594 [patent_doc_number] => 20100148144 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-17 [patent_title] => 'SEMICONDUCTING NANOPARTICLES WITH SURFACE MODIFICATION' [patent_app_type] => utility [patent_app_number] => 11/922790 [patent_app_country] => US [patent_app_date] => 2006-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3812 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20100148144.pdf [firstpage_image] =>[orig_patent_app_number] => 11922790 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/922790
Semiconducting nanoparticles with surface modification Jun 28, 2006 Issued
Array ( [id] => 4614054 [patent_doc_number] => 07989806 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-02 [patent_title] => 'Pixel performance improvement by use of a field-shield' [patent_app_type] => utility [patent_app_number] => 11/993779 [patent_app_country] => US [patent_app_date] => 2006-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 3566 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/989/07989806.pdf [firstpage_image] =>[orig_patent_app_number] => 11993779 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/993779
Pixel performance improvement by use of a field-shield Jun 26, 2006 Issued
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