
Long Pham
Examiner (ID: 16756, Phone: (571)272-1714 , Office: P/2814 )
| Most Active Art Unit | 2814 |
| Art Unit(s) | 2899, 2897, 1107, 2814, 1763, 2812, 2822, 2823 |
| Total Applications | 3709 |
| Issued Applications | 3257 |
| Pending Applications | 178 |
| Abandoned Applications | 335 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 20204152
[patent_doc_number] => 12406936
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-09-02
[patent_title] => Semiconductor package with substrate recess and methods for forming the same
[patent_app_type] => utility
[patent_app_number] => 17/829552
[patent_app_country] => US
[patent_app_date] => 2022-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 28
[patent_no_of_words] => 8816
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17829552
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/829552 | Semiconductor package with substrate recess and methods for forming the same | May 31, 2022 | Issued |
Array
(
[id] => 19341426
[patent_doc_number] => 12051621
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-07-30
[patent_title] => Microelectronic assembly from processed substrate
[patent_app_type] => utility
[patent_app_number] => 17/825405
[patent_app_country] => US
[patent_app_date] => 2022-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 6231
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17825405
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/825405 | Microelectronic assembly from processed substrate | May 25, 2022 | Issued |
Array
(
[id] => 17840728
[patent_doc_number] => 20220278034
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-01
[patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/749218
[patent_app_country] => US
[patent_app_date] => 2022-05-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10924
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17749218
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/749218 | Semiconductor structure and manufacturing method thereof | May 19, 2022 | Issued |
Array
(
[id] => 18857280
[patent_doc_number] => 11854875
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-12-26
[patent_title] => Contact structure of a semiconductor device
[patent_app_type] => utility
[patent_app_number] => 17/664129
[patent_app_country] => US
[patent_app_date] => 2022-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 19
[patent_no_of_words] => 7501
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17664129
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/664129 | Contact structure of a semiconductor device | May 18, 2022 | Issued |
Array
(
[id] => 18798579
[patent_doc_number] => 11832447
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-11-28
[patent_title] => Memory arrays, and methods of forming memory arrays
[patent_app_type] => utility
[patent_app_number] => 17/746671
[patent_app_country] => US
[patent_app_date] => 2022-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 29
[patent_no_of_words] => 8035
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17746671
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/746671 | Memory arrays, and methods of forming memory arrays | May 16, 2022 | Issued |
Array
(
[id] => 18999175
[patent_doc_number] => 11916031
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-02-27
[patent_title] => Semiconductor device and method of manufacturing
[patent_app_type] => utility
[patent_app_number] => 17/745225
[patent_app_country] => US
[patent_app_date] => 2022-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 21
[patent_no_of_words] => 9743
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17745225
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/745225 | Semiconductor device and method of manufacturing | May 15, 2022 | Issued |
Array
(
[id] => 19063187
[patent_doc_number] => 11942439
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-03-26
[patent_title] => Semiconductor package structure
[patent_app_type] => utility
[patent_app_number] => 17/744297
[patent_app_country] => US
[patent_app_date] => 2022-05-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 22
[patent_no_of_words] => 11857
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17744297
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/744297 | Semiconductor package structure | May 12, 2022 | Issued |
Array
(
[id] => 18774329
[patent_doc_number] => 20230369160
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-16
[patent_title] => Semiconductor Device Package Thermally Coupled to Passive Element
[patent_app_type] => utility
[patent_app_number] => 17/742666
[patent_app_country] => US
[patent_app_date] => 2022-05-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6788
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17742666
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/742666 | Semiconductor Device Package Thermally Coupled to Passive Element | May 11, 2022 | Pending |
Array
(
[id] => 18891072
[patent_doc_number] => 11869849
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-01-09
[patent_title] => Semiconductor package with EMI shielding structure
[patent_app_type] => utility
[patent_app_number] => 17/739196
[patent_app_country] => US
[patent_app_date] => 2022-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 4893
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 179
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17739196
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/739196 | Semiconductor package with EMI shielding structure | May 8, 2022 | Issued |
Array
(
[id] => 18269889
[patent_doc_number] => 20230091131
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-23
[patent_title] => SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE
[patent_app_type] => utility
[patent_app_number] => 17/739329
[patent_app_country] => US
[patent_app_date] => 2022-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7870
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17739329
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/739329 | Semiconductor package and method of manufacturing the semiconductor package | May 8, 2022 | Issued |
Array
(
[id] => 17949249
[patent_doc_number] => 20220336268
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-20
[patent_title] => CONTACT FORMATION METHOD AND RELATED STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 17/661734
[patent_app_country] => US
[patent_app_date] => 2022-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11440
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17661734
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/661734 | Contact formation method and related structure | May 1, 2022 | Issued |
Array
(
[id] => 19957319
[patent_doc_number] => 12327736
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-06-10
[patent_title] => Multilayer package substrate with improved current density distribution
[patent_app_type] => utility
[patent_app_number] => 17/733998
[patent_app_country] => US
[patent_app_date] => 2022-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 25
[patent_no_of_words] => 2192
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17733998
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/733998 | Multilayer package substrate with improved current density distribution | Apr 29, 2022 | Issued |
Array
(
[id] => 20332838
[patent_doc_number] => 12463123
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-11-04
[patent_title] => Multi-chip system-in-package
[patent_app_type] => utility
[patent_app_number] => 17/661420
[patent_app_country] => US
[patent_app_date] => 2022-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 29
[patent_no_of_words] => 4380
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17661420
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/661420 | Multi-chip system-in-package | Apr 28, 2022 | Issued |
Array
(
[id] => 20216180
[patent_doc_number] => 12412834
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-09-09
[patent_title] => Triple-sided module
[patent_app_type] => utility
[patent_app_number] => 17/727586
[patent_app_country] => US
[patent_app_date] => 2022-04-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 2143
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17727586
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/727586 | Triple-sided module | Apr 21, 2022 | Issued |
Array
(
[id] => 18142217
[patent_doc_number] => 20230016061
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-01-19
[patent_title] => SEMICONDUCTOR PACKAGE
[patent_app_type] => utility
[patent_app_number] => 17/721745
[patent_app_country] => US
[patent_app_date] => 2022-04-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8166
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17721745
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/721745 | Semiconductor package | Apr 14, 2022 | Issued |
Array
(
[id] => 18320862
[patent_doc_number] => 20230118990
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-04-20
[patent_title] => Multi-Gate Semiconductor Device And Fabrication Method Thereof
[patent_app_type] => utility
[patent_app_number] => 17/721432
[patent_app_country] => US
[patent_app_date] => 2022-04-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11401
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17721432
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/721432 | Multi-Gate Semiconductor Device And Fabrication Method Thereof | Apr 14, 2022 | Pending |
Array
(
[id] => 18126321
[patent_doc_number] => 20230011941
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-01-12
[patent_title] => SEMICONDUCTOR PACKAGE
[patent_app_type] => utility
[patent_app_number] => 17/718662
[patent_app_country] => US
[patent_app_date] => 2022-04-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7097
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17718662
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/718662 | Semiconductor package | Apr 11, 2022 | Issued |
Array
(
[id] => 17765112
[patent_doc_number] => 20220238725
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-07-28
[patent_title] => Self-Aligned Spacers For Multi-Gate Devices And Method Of Fabrication Thereof
[patent_app_type] => utility
[patent_app_number] => 17/717477
[patent_app_country] => US
[patent_app_date] => 2022-04-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11733
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17717477
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/717477 | Self-aligned spacers for multi-gate devices and method of fabrication thereof | Apr 10, 2022 | Issued |
Array
(
[id] => 17752840
[patent_doc_number] => 20220231045
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-07-21
[patent_title] => METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/658410
[patent_app_country] => US
[patent_app_date] => 2022-04-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6818
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17658410
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/658410 | Method for manufacturing semiconductor memory device and semiconductor memory device | Apr 6, 2022 | Issued |
Array
(
[id] => 18696405
[patent_doc_number] => 20230326843
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-10-12
[patent_title] => ELECTRIC CONTACT STRUCTURE FOR THREE-DIMENSIONAL CHIP PACKAGE MODULE
[patent_app_type] => utility
[patent_app_number] => 17/715056
[patent_app_country] => US
[patent_app_date] => 2022-04-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1258
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -2
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17715056
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/715056 | ELECTRIC CONTACT STRUCTURE FOR THREE-DIMENSIONAL CHIP PACKAGE MODULE | Apr 6, 2022 | Abandoned |