
Long Pham
Examiner (ID: 5269, Phone: (571)272-1714 , Office: P/2814 )
| Most Active Art Unit | 2814 |
| Art Unit(s) | 2822, 2899, 2897, 2823, 1107, 2814, 2812, 1763 |
| Total Applications | 3774 |
| Issued Applications | 3306 |
| Pending Applications | 160 |
| Abandoned Applications | 335 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 606783
[patent_doc_number] => 07154149
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-12-26
[patent_title] => 'EDS protection configuration and method for light emitting diodes'
[patent_app_type] => utility
[patent_app_number] => 10/791709
[patent_app_country] => US
[patent_app_date] => 2004-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 1979
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/154/07154149.pdf
[firstpage_image] =>[orig_patent_app_number] => 10791709
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/791709 | EDS protection configuration and method for light emitting diodes | Mar 3, 2004 | Issued |
Array
(
[id] => 785201
[patent_doc_number] => 06989298
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-01-24
[patent_title] => 'Method of forming thin-film transistor devices with electro-static discharge protection'
[patent_app_type] => utility
[patent_app_number] => 10/794219
[patent_app_country] => US
[patent_app_date] => 2004-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 11
[patent_no_of_words] => 4369
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/989/06989298.pdf
[firstpage_image] =>[orig_patent_app_number] => 10794219
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/794219 | Method of forming thin-film transistor devices with electro-static discharge protection | Mar 3, 2004 | Issued |
Array
(
[id] => 941238
[patent_doc_number] => 06969629
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-11-29
[patent_title] => 'Method for manufacturing micro-structural unit'
[patent_app_type] => utility
[patent_app_number] => 10/791903
[patent_app_country] => US
[patent_app_date] => 2004-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 88
[patent_no_of_words] => 23010
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 228
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/969/06969629.pdf
[firstpage_image] =>[orig_patent_app_number] => 10791903
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/791903 | Method for manufacturing micro-structural unit | Mar 3, 2004 | Issued |
Array
(
[id] => 508601
[patent_doc_number] => 07198987
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-04-03
[patent_title] => 'Overmolded semiconductor package with an integrated EMI and RFI shield'
[patent_app_type] => utility
[patent_app_number] => 10/793618
[patent_app_country] => US
[patent_app_date] => 2004-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3795
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/198/07198987.pdf
[firstpage_image] =>[orig_patent_app_number] => 10793618
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/793618 | Overmolded semiconductor package with an integrated EMI and RFI shield | Mar 3, 2004 | Issued |
Array
(
[id] => 7405448
[patent_doc_number] => 20040262785
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-30
[patent_title] => 'Terminal structure of multi-layer substrate and method for forming the same'
[patent_app_type] => new
[patent_app_number] => 10/791718
[patent_app_country] => US
[patent_app_date] => 2004-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3820
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0262/20040262785.pdf
[firstpage_image] =>[orig_patent_app_number] => 10791718
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/791718 | Terminal structure of multi-layer substrate and method for forming the same | Mar 3, 2004 | Abandoned |
Array
(
[id] => 7083274
[patent_doc_number] => 20050048654
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-03
[patent_title] => 'Method of evaluating reticle pattern overlay registration'
[patent_app_type] => utility
[patent_app_number] => 10/792345
[patent_app_country] => US
[patent_app_date] => 2004-03-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 3628
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0048/20050048654.pdf
[firstpage_image] =>[orig_patent_app_number] => 10792345
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/792345 | Method of evaluating reticle pattern overlay registration | Mar 2, 2004 | Issued |
Array
(
[id] => 672982
[patent_doc_number] => 07091557
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-08-15
[patent_title] => 'Semiconductor component with increased dielectric strength and/or reduced on resistance'
[patent_app_type] => utility
[patent_app_number] => 10/790979
[patent_app_country] => US
[patent_app_date] => 2004-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 12
[patent_no_of_words] => 9299
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 38
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/091/07091557.pdf
[firstpage_image] =>[orig_patent_app_number] => 10790979
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/790979 | Semiconductor component with increased dielectric strength and/or reduced on resistance | Mar 1, 2004 | Issued |
Array
(
[id] => 474118
[patent_doc_number] => 07230341
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-06-12
[patent_title] => 'Electronic device and method of manufacturing the same, circuit board, and electronic instrument'
[patent_app_type] => utility
[patent_app_number] => 10/788449
[patent_app_country] => US
[patent_app_date] => 2004-03-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 19
[patent_no_of_words] => 5811
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/230/07230341.pdf
[firstpage_image] =>[orig_patent_app_number] => 10788449
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/788449 | Electronic device and method of manufacturing the same, circuit board, and electronic instrument | Feb 29, 2004 | Issued |
Array
(
[id] => 363403
[patent_doc_number] => 07482214
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-01-27
[patent_title] => 'Transistor design and layout for performance improvement with strain'
[patent_app_type] => utility
[patent_app_number] => 10/785648
[patent_app_country] => US
[patent_app_date] => 2004-02-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 4362
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/482/07482214.pdf
[firstpage_image] =>[orig_patent_app_number] => 10785648
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/785648 | Transistor design and layout for performance improvement with strain | Feb 23, 2004 | Issued |
Array
(
[id] => 5602494
[patent_doc_number] => 20060292839
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-12-28
[patent_title] => 'Contacts fabric using heterostructure of metal/semiconductor nanorods and fabrication method thereof'
[patent_app_type] => utility
[patent_app_number] => 10/558899
[patent_app_country] => US
[patent_app_date] => 2004-02-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3271
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0292/20060292839.pdf
[firstpage_image] =>[orig_patent_app_number] => 10558899
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/558899 | Contacts fabric using heterostructure of metal/semiconductor nanorods and fabrication method thereof | Feb 23, 2004 | Abandoned |
Array
(
[id] => 7448074
[patent_doc_number] => 20040164352
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-08-26
[patent_title] => 'Active matrix pixel device construction method'
[patent_app_type] => new
[patent_app_number] => 10/785494
[patent_app_country] => US
[patent_app_date] => 2004-02-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4708
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 18
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0164/20040164352.pdf
[firstpage_image] =>[orig_patent_app_number] => 10785494
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/785494 | Active matrix pixel device construction method | Feb 23, 2004 | Issued |
Array
(
[id] => 7447598
[patent_doc_number] => 20040164303
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-08-26
[patent_title] => 'Contact between element to be driven and thin film transistor for supplying power to element to be driven'
[patent_app_type] => new
[patent_app_number] => 10/785578
[patent_app_country] => US
[patent_app_date] => 2004-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 13124
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0164/20040164303.pdf
[firstpage_image] =>[orig_patent_app_number] => 10785578
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/785578 | Contact between element to be driven and thin film transistor for supplying power to element to be driven | Feb 22, 2004 | Issued |
Array
(
[id] => 7429556
[patent_doc_number] => 20040161949
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-08-19
[patent_title] => 'Semiconductor and device nanotechnology and methods for their manufacture'
[patent_app_type] => new
[patent_app_number] => 10/783629
[patent_app_country] => US
[patent_app_date] => 2004-02-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 9395
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0161/20040161949.pdf
[firstpage_image] =>[orig_patent_app_number] => 10783629
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/783629 | Semiconductor and device nanotechnology and methods for their manufacture | Feb 19, 2004 | Issued |
Array
(
[id] => 401186
[patent_doc_number] => 07291550
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-11-06
[patent_title] => 'Method to form a contact hole'
[patent_app_type] => utility
[patent_app_number] => 10/778293
[patent_app_country] => US
[patent_app_date] => 2004-02-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 3462
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/291/07291550.pdf
[firstpage_image] =>[orig_patent_app_number] => 10778293
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/778293 | Method to form a contact hole | Feb 12, 2004 | Issued |
Array
(
[id] => 1093838
[patent_doc_number] => 06825492
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-11-30
[patent_title] => 'Method of manufacturing a semiconductor device'
[patent_app_type] => B2
[patent_app_number] => 10/775128
[patent_app_country] => US
[patent_app_date] => 2004-02-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 46
[patent_no_of_words] => 22031
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/825/06825492.pdf
[firstpage_image] =>[orig_patent_app_number] => 10775128
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/775128 | Method of manufacturing a semiconductor device | Feb 10, 2004 | Issued |
Array
(
[id] => 449861
[patent_doc_number] => 07250678
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-07-31
[patent_title] => 'Copper-containing C4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same'
[patent_app_type] => utility
[patent_app_number] => 10/776448
[patent_app_country] => US
[patent_app_date] => 2004-02-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 17
[patent_no_of_words] => 6336
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/250/07250678.pdf
[firstpage_image] =>[orig_patent_app_number] => 10776448
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/776448 | Copper-containing C4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same | Feb 9, 2004 | Issued |
Array
(
[id] => 256729
[patent_doc_number] => 07576406
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-08-18
[patent_title] => 'Semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 10/773658
[patent_app_country] => US
[patent_app_date] => 2004-02-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 25
[patent_no_of_words] => 10185
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/576/07576406.pdf
[firstpage_image] =>[orig_patent_app_number] => 10773658
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/773658 | Semiconductor device | Feb 8, 2004 | Issued |
Array
(
[id] => 7219388
[patent_doc_number] => 20040155253
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-08-12
[patent_title] => 'Single electron transistor having memory function and method of manufacturing the same'
[patent_app_type] => new
[patent_app_number] => 10/773288
[patent_app_country] => US
[patent_app_date] => 2004-02-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 9290
[patent_no_of_claims] => 43
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0155/20040155253.pdf
[firstpage_image] =>[orig_patent_app_number] => 10773288
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/773288 | Single electron transistor having memory function | Feb 8, 2004 | Issued |
Array
(
[id] => 7264184
[patent_doc_number] => 20040242017
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-02
[patent_title] => 'Etchant for signal wire and method of manufacturing thin film transistor array panel using etchant'
[patent_app_type] => new
[patent_app_number] => 10/772293
[patent_app_country] => US
[patent_app_date] => 2004-02-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 42
[patent_figures_cnt] => 42
[patent_no_of_words] => 8502
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0242/20040242017.pdf
[firstpage_image] =>[orig_patent_app_number] => 10772293
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/772293 | Etchant for signal wire and method of manufacturing thin film transistor array panel using etchant | Feb 5, 2004 | Issued |
Array
(
[id] => 7219678
[patent_doc_number] => 20040155301
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-08-12
[patent_title] => 'Three-dimensional-memory-based self-test integrated circuits and methods'
[patent_app_type] => new
[patent_app_number] => 10/772053
[patent_app_country] => US
[patent_app_date] => 2004-02-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 23
[patent_no_of_words] => 25519
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 59
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0155/20040155301.pdf
[firstpage_image] =>[orig_patent_app_number] => 10772053
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/772053 | Three-dimensional-memory-based self-test integrated circuits and methods | Feb 2, 2004 | Issued |