
Long Pham
Examiner (ID: 5269, Phone: (571)272-1714 , Office: P/2814 )
| Most Active Art Unit | 2814 |
| Art Unit(s) | 2822, 2899, 2897, 2823, 1107, 2814, 2812, 1763 |
| Total Applications | 3774 |
| Issued Applications | 3306 |
| Pending Applications | 160 |
| Abandoned Applications | 335 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7147498
[patent_doc_number] => 20050023518
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-03
[patent_title] => 'Superconducting digital first-in first-out buffer using physical back pressure mechanism'
[patent_app_type] => utility
[patent_app_number] => 10/628779
[patent_app_country] => US
[patent_app_date] => 2003-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3687
[patent_no_of_claims] => 20
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0023/20050023518.pdf
[firstpage_image] =>[orig_patent_app_number] => 10628779
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/628779 | Superconducting digital first-in first-out buffer using physical back pressure mechanism | Jul 27, 2003 | Issued |
Array
(
[id] => 1046717
[patent_doc_number] => 06864111
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-03-08
[patent_title] => 'Column-row addressable electric microswitch arrays and sensor matrices employing them'
[patent_app_type] => utility
[patent_app_number] => 10/628009
[patent_app_country] => US
[patent_app_date] => 2003-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
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[patent_no_of_words] => 10524
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/864/06864111.pdf
[firstpage_image] =>[orig_patent_app_number] => 10628009
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/628009 | Column-row addressable electric microswitch arrays and sensor matrices employing them | Jul 24, 2003 | Issued |
Array
(
[id] => 7368521
[patent_doc_number] => 20040026712
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-02-12
[patent_title] => 'Three terminal edge illuminated epilayer waveguide phototransistor'
[patent_app_type] => new
[patent_app_number] => 10/626979
[patent_app_country] => US
[patent_app_date] => 2003-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_no_of_words] => 2607
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0026/20040026712.pdf
[firstpage_image] =>[orig_patent_app_number] => 10626979
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/626979 | Three terminal edge illuminated epilayer waveguide phototransistor | Jul 24, 2003 | Abandoned |
Array
(
[id] => 7291858
[patent_doc_number] => 20040212095
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-28
[patent_title] => 'Method for forming contact openings on a MOS integrated circuit'
[patent_app_type] => new
[patent_app_number] => 10/624849
[patent_app_country] => US
[patent_app_date] => 2003-07-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2695
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0212/20040212095.pdf
[firstpage_image] =>[orig_patent_app_number] => 10624849
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/624849 | Method for forming contact openings on a MOS integrated circuit | Jul 21, 2003 | Issued |
Array
(
[id] => 7675158
[patent_doc_number] => 20040126960
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-07-01
[patent_title] => 'Merged memory and logic semiconductor device of salicided dual gate structure including embedded memory of self-aligned contact structure and manufacturing method thereof'
[patent_app_type] => new
[patent_app_number] => 10/623587
[patent_app_country] => US
[patent_app_date] => 2003-07-22
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 7195
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[pdf_file] => publications/A1/0126/20040126960.pdf
[firstpage_image] =>[orig_patent_app_number] => 10623587
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/623587 | Merged memory and logic semiconductor device of salicided dual gate structure including embedded memory of self-aligned contact structure and manufacturing method thereof | Jul 21, 2003 | Issued |
Array
(
[id] => 7388060
[patent_doc_number] => 20040016927
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-01-29
[patent_title] => 'Thin film transistor, liquid crystal display substrate, and their manufacture methods'
[patent_app_type] => new
[patent_app_number] => 10/624074
[patent_app_country] => US
[patent_app_date] => 2003-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
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[patent_no_of_words] => 7951
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[pdf_file] => publications/A1/0016/20040016927.pdf
[firstpage_image] =>[orig_patent_app_number] => 10624074
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/624074 | Thin film transistor, liquid crystal display substrate, and their manufacture methods | Jul 20, 2003 | Issued |
Array
(
[id] => 1140799
[patent_doc_number] => 06781171
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-08-24
[patent_title] => 'Pinned photodiode for a CMOS image sensor and fabricating method thereof'
[patent_app_type] => B2
[patent_app_number] => 10/623389
[patent_app_country] => US
[patent_app_date] => 2003-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 1340
[patent_no_of_claims] => 7
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/781/06781171.pdf
[firstpage_image] =>[orig_patent_app_number] => 10623389
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/623389 | Pinned photodiode for a CMOS image sensor and fabricating method thereof | Jul 17, 2003 | Issued |
Array
(
[id] => 1025594
[patent_doc_number] => 06885103
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-04-26
[patent_title] => 'Semiconductor device including ternary phase diffusion barrier'
[patent_app_type] => utility
[patent_app_number] => 10/620608
[patent_app_country] => US
[patent_app_date] => 2003-07-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 2618
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[pdf_file] => patents/06/885/06885103.pdf
[firstpage_image] =>[orig_patent_app_number] => 10620608
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/620608 | Semiconductor device including ternary phase diffusion barrier | Jul 16, 2003 | Issued |
Array
(
[id] => 7130157
[patent_doc_number] => 20040041186
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-03-04
[patent_title] => 'Ferroelectric transistor with enhanced data retention'
[patent_app_type] => new
[patent_app_number] => 10/620979
[patent_app_country] => US
[patent_app_date] => 2003-07-16
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[patent_drawing_sheets_cnt] => 22
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[pdf_file] => publications/A1/0041/20040041186.pdf
[firstpage_image] =>[orig_patent_app_number] => 10620979
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/620979 | Ferroelectric transistor with enhanced data retention | Jul 15, 2003 | Issued |
Array
(
[id] => 7120319
[patent_doc_number] => 20050012148
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-01-20
[patent_title] => 'TRANSISTOR WITH IMPROVED SAFE OPERATING AREA'
[patent_app_type] => utility
[patent_app_number] => 10/619699
[patent_app_country] => US
[patent_app_date] => 2003-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[pdf_file] => publications/A1/0012/20050012148.pdf
[firstpage_image] =>[orig_patent_app_number] => 10619699
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/619699 | Transistor with improved safe operating area | Jul 14, 2003 | Issued |
Array
(
[id] => 7351228
[patent_doc_number] => 20040012732
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-01-22
[patent_title] => 'Illumination device and liquid crystal display device'
[patent_app_type] => new
[patent_app_number] => 10/619959
[patent_app_country] => US
[patent_app_date] => 2003-07-14
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[pdf_file] => publications/A1/0012/20040012732.pdf
[firstpage_image] =>[orig_patent_app_number] => 10619959
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/619959 | Illumination device and liquid crystal display device | Jul 13, 2003 | Issued |
Array
(
[id] => 422142
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[patent_issue_date] => 2007-09-25
[patent_title] => 'Semiconductor integrated circuit device'
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[patent_app_number] => 10/619039
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/619039 | Semiconductor integrated circuit device | Jul 13, 2003 | Issued |
Array
(
[id] => 7427400
[patent_doc_number] => 20040007737
[patent_country] => US
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[patent_issue_date] => 2004-01-15
[patent_title] => 'Ultra small size vertical MOSFET device and method for the manufacture thereof'
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[pdf_file] => publications/A1/0007/20040007737.pdf
[firstpage_image] =>[orig_patent_app_number] => 10617183
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/617183 | Ultra small size vertical MOSFET device and method for the manufacture thereof | Jul 10, 2003 | Issued |
Array
(
[id] => 742642
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[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-04-18
[patent_title] => 'Micro electro mechanical system apparatus'
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[pdf_file] => patents/07/030/07030416.pdf
[firstpage_image] =>[orig_patent_app_number] => 10618258
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/618258 | Micro electro mechanical system apparatus | Jul 10, 2003 | Issued |
Array
(
[id] => 7086558
[patent_doc_number] => 20050006670
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-01-13
[patent_title] => 'LIBRARY OF CELLS FOR USE IN DESIGNING SETS OF DOMINO LOGIC CIRCUITS IN A STANDARD CELL LIBRARY, OR THE LIKE, AND METHOD FOR USING SAME'
[patent_app_type] => utility
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[firstpage_image] =>[orig_patent_app_number] => 10604318
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/604318 | Library of cells for use in designing sets of domino logic circuits in a standard cell library, or the like, and method for using same | Jul 9, 2003 | Issued |
Array
(
[id] => 7089116
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[patent_title] => 'Solution deposition of chalcogenide films'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/617118 | Solution deposition of chalcogenide films | Jul 9, 2003 | Issued |
Array
(
[id] => 682457
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[patent_title] => 'Aluminum cap with electroless nickel/immersion gold'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/616268 | Aluminum cap with electroless nickel/immersion gold | Jul 8, 2003 | Issued |
Array
(
[id] => 7396527
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/614778 | Method for producing a nitride semiconductor element | Jul 8, 2003 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/615238 | Method for fabricating high voltage and low voltage transistors | Jul 8, 2003 | Issued |
Array
(
[id] => 7383330
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[firstpage_image] =>[orig_patent_app_number] => 10612988
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/612988 | Semiconductor device with an improved gate electrode pattern and a method of manufacturing the same | Jul 6, 2003 | Issued |