
Long Pham
Examiner (ID: 5269, Phone: (571)272-1714 , Office: P/2814 )
| Most Active Art Unit | 2814 |
| Art Unit(s) | 2822, 2899, 2897, 2823, 1107, 2814, 2812, 1763 |
| Total Applications | 3774 |
| Issued Applications | 3306 |
| Pending Applications | 160 |
| Abandoned Applications | 335 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5968528
[patent_doc_number] => 20020090788
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-07-11
[patent_title] => 'Method for independent control of polycrystalline silicon-germanium in a silicon-germanium HBT and related structure'
[patent_app_type] => new
[patent_app_number] => 10/054438
[patent_app_country] => US
[patent_app_date] => 2002-01-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 6247
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0090/20020090788.pdf
[firstpage_image] =>[orig_patent_app_number] => 10054438
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/054438 | Independent control of polycrystalline silicon-germanium in an HBT and related structure | Jan 21, 2002 | Issued |
Array
(
[id] => 1375867
[patent_doc_number] => 06559022
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-05-06
[patent_title] => 'Method for independent control of polycrystalline silicon-germanium in an HBT'
[patent_app_type] => B2
[patent_app_number] => 10/053980
[patent_app_country] => US
[patent_app_date] => 2002-01-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 6214
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/559/06559022.pdf
[firstpage_image] =>[orig_patent_app_number] => 10053980
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/053980 | Method for independent control of polycrystalline silicon-germanium in an HBT | Jan 21, 2002 | Issued |
Array
(
[id] => 1570287
[patent_doc_number] => 06498093
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-12-24
[patent_title] => 'Formation without vacuum break of sacrificial layer that dissolves in acidic activation solution within interconnect'
[patent_app_type] => B1
[patent_app_number] => 10/052133
[patent_app_country] => US
[patent_app_date] => 2002-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 16
[patent_no_of_words] => 4665
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 237
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/498/06498093.pdf
[firstpage_image] =>[orig_patent_app_number] => 10052133
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/052133 | Formation without vacuum break of sacrificial layer that dissolves in acidic activation solution within interconnect | Jan 16, 2002 | Issued |
Array
(
[id] => 7301164
[patent_doc_number] => 20040113141
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-06-17
[patent_title] => 'Nitride semiconductor laser element and optical device containing it'
[patent_app_type] => new
[patent_app_number] => 10/466339
[patent_app_country] => US
[patent_app_date] => 2003-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 16354
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0113/20040113141.pdf
[firstpage_image] =>[orig_patent_app_number] => 10466339
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/466339 | Nitride semiconductor laser element and optical device containing it | Jan 8, 2002 | Issued |
Array
(
[id] => 1112830
[patent_doc_number] => 06803248
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-10-12
[patent_title] => 'Chemistry for etching quaternary interface layers on InGaAsP mostly formed between GaAs and InxGa(1-x)P layers'
[patent_app_type] => B2
[patent_app_number] => 10/029093
[patent_app_country] => US
[patent_app_date] => 2001-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 12
[patent_no_of_words] => 6217
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 52
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/803/06803248.pdf
[firstpage_image] =>[orig_patent_app_number] => 10029093
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/029093 | Chemistry for etching quaternary interface layers on InGaAsP mostly formed between GaAs and InxGa(1-x)P layers | Dec 20, 2001 | Issued |
Array
(
[id] => 6306512
[patent_doc_number] => 20020094592
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-07-18
[patent_title] => 'Fabrication method of liquid crystal display device for an attachment process'
[patent_app_type] => new
[patent_app_number] => 10/024283
[patent_app_country] => US
[patent_app_date] => 2001-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3247
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 43
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0094/20020094592.pdf
[firstpage_image] =>[orig_patent_app_number] => 10024283
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/024283 | Fabrication method of liquid crystal display device for an attachment process | Dec 20, 2001 | Issued |
Array
(
[id] => 7634807
[patent_doc_number] => 06656811
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-12-02
[patent_title] => 'Carbide emitter mask etch stop'
[patent_app_type] => B2
[patent_app_number] => 10/036763
[patent_app_country] => US
[patent_app_date] => 2001-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 17
[patent_no_of_words] => 7884
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 12
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/656/06656811.pdf
[firstpage_image] =>[orig_patent_app_number] => 10036763
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/036763 | Carbide emitter mask etch stop | Dec 20, 2001 | Issued |
Array
(
[id] => 6629620
[patent_doc_number] => 20020086455
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-07-04
[patent_title] => 'Method for the manufacture of micro-mechanical components'
[patent_app_type] => new
[patent_app_number] => 10/027044
[patent_app_country] => US
[patent_app_date] => 2001-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 8014
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0086/20020086455.pdf
[firstpage_image] =>[orig_patent_app_number] => 10027044
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/027044 | Method for the manufacture of micro-mechanical components | Dec 19, 2001 | Issued |
Array
(
[id] => 6683382
[patent_doc_number] => 20030119246
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-06-26
[patent_title] => 'Low-temperature grown high quality ultra-thin CoTiO3 gate dielectrics'
[patent_app_type] => new
[patent_app_number] => 10/028643
[patent_app_country] => US
[patent_app_date] => 2001-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5327
[patent_no_of_claims] => 55
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 40
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0119/20030119246.pdf
[firstpage_image] =>[orig_patent_app_number] => 10028643
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/028643 | Low-temperature grown high quality ultra-thin CoTiO3 gate dielectrics | Dec 19, 2001 | Issued |
Array
(
[id] => 6668992
[patent_doc_number] => 20030113976
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-06-19
[patent_title] => 'Wafer-bonding using solder and method of making the same'
[patent_app_type] => new
[patent_app_number] => 10/015618
[patent_app_country] => US
[patent_app_date] => 2001-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 4080
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 47
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0113/20030113976.pdf
[firstpage_image] =>[orig_patent_app_number] => 10015618
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/015618 | Wafer-bonding using solder and method of making the same | Dec 16, 2001 | Issued |
Array
(
[id] => 7643929
[patent_doc_number] => 06429109
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-08-06
[patent_title] => 'Method to form high k dielectric and silicide to reduce poly depletion by using a sacrificial metal between oxide and gate'
[patent_app_type] => B1
[patent_app_number] => 10/017953
[patent_app_country] => US
[patent_app_date] => 2001-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 3
[patent_no_of_words] => 1505
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 11
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/429/06429109.pdf
[firstpage_image] =>[orig_patent_app_number] => 10017953
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/017953 | Method to form high k dielectric and silicide to reduce poly depletion by using a sacrificial metal between oxide and gate | Dec 13, 2001 | Issued |
Array
(
[id] => 1112915
[patent_doc_number] => 06803282
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-10-12
[patent_title] => 'Methods for fabricating low CHC degradation mosfet transistors'
[patent_app_type] => B2
[patent_app_number] => 10/020034
[patent_app_country] => US
[patent_app_date] => 2001-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 5873
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/803/06803282.pdf
[firstpage_image] =>[orig_patent_app_number] => 10020034
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/020034 | Methods for fabricating low CHC degradation mosfet transistors | Dec 6, 2001 | Issued |
Array
(
[id] => 6469346
[patent_doc_number] => 20020151125
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-10-17
[patent_title] => 'Method of forming a CMOS type semiconductor device having dual gates'
[patent_app_type] => new
[patent_app_number] => 10/006093
[patent_app_country] => US
[patent_app_date] => 2001-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4014
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 188
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0151/20020151125.pdf
[firstpage_image] =>[orig_patent_app_number] => 10006093
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/006093 | Method of forming a CMOS type semiconductor device having dual gates | Dec 5, 2001 | Issued |
Array
(
[id] => 6630507
[patent_doc_number] => 20020086497
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-07-04
[patent_title] => 'Beaker shape trench with nitride pull-back for STI'
[patent_app_type] => new
[patent_app_number] => 10/006574
[patent_app_country] => US
[patent_app_date] => 2001-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2613
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0086/20020086497.pdf
[firstpage_image] =>[orig_patent_app_number] => 10006574
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/006574 | Beaker shape trench with nitride pull-back for STI | Dec 5, 2001 | Abandoned |
Array
(
[id] => 540151
[patent_doc_number] => 07176565
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-02-13
[patent_title] => 'Capacitors having separate terminals on three or more sides'
[patent_app_type] => utility
[patent_app_number] => 10/006188
[patent_app_country] => US
[patent_app_date] => 2001-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 20
[patent_no_of_words] => 7453
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 200
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/176/07176565.pdf
[firstpage_image] =>[orig_patent_app_number] => 10006188
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/006188 | Capacitors having separate terminals on three or more sides | Dec 2, 2001 | Issued |
Array
(
[id] => 5828692
[patent_doc_number] => 20020068398
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-06-06
[patent_title] => 'Method of manufacturing flash memory cell'
[patent_app_type] => new
[patent_app_number] => 09/998314
[patent_app_country] => US
[patent_app_date] => 2001-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1865
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0068/20020068398.pdf
[firstpage_image] =>[orig_patent_app_number] => 09998314
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/998314 | Method of manufacturing flash memory cell | Dec 2, 2001 | Abandoned |
Array
(
[id] => 1578255
[patent_doc_number] => 06448170
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-10
[patent_title] => 'Method of producing external connector for substrate'
[patent_app_type] => B1
[patent_app_number] => 09/998453
[patent_app_country] => US
[patent_app_date] => 2001-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 14
[patent_no_of_words] => 2002
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/448/06448170.pdf
[firstpage_image] =>[orig_patent_app_number] => 09998453
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/998453 | Method of producing external connector for substrate | Nov 26, 2001 | Issued |
Array
(
[id] => 6801300
[patent_doc_number] => 20030096465
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-05-22
[patent_title] => 'Hard mask trimming with thin hard mask layer and top protection layer'
[patent_app_type] => new
[patent_app_number] => 09/996864
[patent_app_country] => US
[patent_app_date] => 2001-11-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 2786
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0096/20030096465.pdf
[firstpage_image] =>[orig_patent_app_number] => 09996864
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/996864 | Hard mask trimming with thin hard mask layer and top protection layer | Nov 18, 2001 | Abandoned |
| 09/986997 | Method for fabricating semiconductor device having group III nitride | Nov 12, 2001 | Abandoned |
Array
(
[id] => 677042
[patent_doc_number] => 07087941
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-08-08
[patent_title] => 'lll-phosphide light emitting devices with thin active layers'
[patent_app_type] => utility
[patent_app_number] => 10/011521
[patent_app_country] => US
[patent_app_date] => 2001-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 15
[patent_no_of_words] => 8654
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/087/07087941.pdf
[firstpage_image] =>[orig_patent_app_number] => 10011521
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/011521 | lll-phosphide light emitting devices with thin active layers | Nov 4, 2001 | Issued |