
Long Pham
Examiner (ID: 5269, Phone: (571)272-1714 , Office: P/2814 )
| Most Active Art Unit | 2814 |
| Art Unit(s) | 2822, 2899, 2897, 2823, 1107, 2814, 2812, 1763 |
| Total Applications | 3774 |
| Issued Applications | 3306 |
| Pending Applications | 160 |
| Abandoned Applications | 335 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1415299
[patent_doc_number] => 06511884
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-01-28
[patent_title] => 'Method to form and/or isolate vertical transistors'
[patent_app_type] => B1
[patent_app_number] => 09/972503
[patent_app_country] => US
[patent_app_date] => 2001-10-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 9
[patent_no_of_words] => 1590
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/511/06511884.pdf
[firstpage_image] =>[orig_patent_app_number] => 09972503
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/972503 | Method to form and/or isolate vertical transistors | Oct 8, 2001 | Issued |
Array
(
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[patent_doc_number] => 06562710
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-05-13
[patent_title] => 'Semiconductor device and method for fabricating the same'
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[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/562/06562710.pdf
[firstpage_image] =>[orig_patent_app_number] => 09971734
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/971734 | Semiconductor device and method for fabricating the same | Oct 8, 2001 | Issued |
Array
(
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[patent_doc_number] => 20020022353
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[patent_kind] => A1
[patent_issue_date] => 2002-02-21
[patent_title] => 'Semiconductor device and manufacturing method thereof'
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[patent_app_date] => 2001-10-09
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[patent_drawing_sheets_cnt] => 4
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Array
(
[id] => 6458844
[patent_doc_number] => 20020020847
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-02-21
[patent_title] => 'Compound semiconductor light emitting device and method of fabricating the same'
[patent_app_type] => new
[patent_app_number] => 09/968802
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[patent_app_date] => 2001-10-03
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[patent_drawing_sheets_cnt] => 15
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[pdf_file] => publications/A1/0020/20020020847.pdf
[firstpage_image] =>[orig_patent_app_number] => 09968802
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/968802 | Compound semiconductor light emitting device and method of fabricating the same | Oct 2, 2001 | Issued |
Array
(
[id] => 1416363
[patent_doc_number] => 06509232
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-01-21
[patent_title] => 'Formation of STI (shallow trench isolation) structures within core and periphery areas of flash memory device'
[patent_app_type] => B1
[patent_app_number] => 09/969573
[patent_app_country] => US
[patent_app_date] => 2001-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
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[pdf_file] => patents/06/509/06509232.pdf
[firstpage_image] =>[orig_patent_app_number] => 09969573
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/969573 | Formation of STI (shallow trench isolation) structures within core and periphery areas of flash memory device | Sep 30, 2001 | Issued |
Array
(
[id] => 1284925
[patent_doc_number] => 06638798
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[patent_issue_date] => 2003-10-28
[patent_title] => 'Method of fabricating a semiconductor device of high-voltage CMOS structure'
[patent_app_type] => B2
[patent_app_number] => 09/964393
[patent_app_country] => US
[patent_app_date] => 2001-09-28
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/964393 | Method of fabricating a semiconductor device of high-voltage CMOS structure | Sep 27, 2001 | Issued |
Array
(
[id] => 6674452
[patent_doc_number] => 20030060055
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[patent_kind] => A1
[patent_issue_date] => 2003-03-27
[patent_title] => 'Resist pattern, a method for fabricating a resist pattern, a method for patterning a thin film and a method for manufacturing a micro device'
[patent_app_type] => new
[patent_app_number] => 09/964433
[patent_app_country] => US
[patent_app_date] => 2001-09-28
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 09964433
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/964433 | Resist pattern, a method for fabricating a resist pattern, a method for patterning a thin film and a method for manufacturing a micro device | Sep 27, 2001 | Abandoned |
Array
(
[id] => 6783120
[patent_doc_number] => 20030064567
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-04-03
[patent_title] => 'Vertical replacement-gate silicon-on-insulator transistor'
[patent_app_type] => new
[patent_app_number] => 09/968234
[patent_app_country] => US
[patent_app_date] => 2001-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
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[pdf_file] => publications/A1/0064/20030064567.pdf
[firstpage_image] =>[orig_patent_app_number] => 09968234
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/968234 | Vertical replacement-gate silicon-on-insulator transistor | Sep 27, 2001 | Issued |
Array
(
[id] => 1383943
[patent_doc_number] => 06559477
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-05-06
[patent_title] => 'Flat panel display device and method for manufacturing the same'
[patent_app_type] => B2
[patent_app_number] => 09/964403
[patent_app_country] => US
[patent_app_date] => 2001-09-28
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/964403 | Flat panel display device and method for manufacturing the same | Sep 27, 2001 | Issued |
Array
(
[id] => 1196692
[patent_doc_number] => 06727165
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[patent_kind] => B1
[patent_issue_date] => 2004-04-27
[patent_title] => 'Fabrication of metal contacts for deep-submicron technologies'
[patent_app_type] => B1
[patent_app_number] => 09/967074
[patent_app_country] => US
[patent_app_date] => 2001-09-28
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/967074 | Fabrication of metal contacts for deep-submicron technologies | Sep 27, 2001 | Issued |
Array
(
[id] => 6063594
[patent_doc_number] => 20020031889
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[patent_issue_date] => 2002-03-14
[patent_title] => 'Method for manufacturing a semiconductor device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/964643 | Method for manufacturing a semiconductor device | Sep 27, 2001 | Abandoned |
Array
(
[id] => 1155459
[patent_doc_number] => 06764888
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[patent_issue_date] => 2004-07-20
[patent_title] => 'Method of producing nitride-based heterostructure devices'
[patent_app_type] => B2
[patent_app_number] => 09/966563
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/966563 | Method of producing nitride-based heterostructure devices | Sep 26, 2001 | Issued |
Array
(
[id] => 6469431
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[patent_title] => 'Method for semiconductor device planarization'
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Array
(
[id] => 1180868
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[patent_title] => 'Complementary MISFET'
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Array
(
[id] => 7631383
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[patent_title] => 'Method of producing exposure mask'
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Array
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Array
(
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Array
(
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Array
(
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/932863 | Method of simultaneous formation of local interconnect and gate electrode | Aug 16, 2001 | Abandoned |