
Long Pham
Examiner (ID: 5269, Phone: (571)272-1714 , Office: P/2814 )
| Most Active Art Unit | 2814 |
| Art Unit(s) | 2822, 2899, 2897, 2823, 1107, 2814, 2812, 1763 |
| Total Applications | 3774 |
| Issued Applications | 3306 |
| Pending Applications | 160 |
| Abandoned Applications | 335 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1571155
[patent_doc_number] => 06498371
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-12-24
[patent_title] => 'Body-tied-to-body SOI CMOS inverter circuit'
[patent_app_type] => B1
[patent_app_number] => 09/919543
[patent_app_country] => US
[patent_app_date] => 2001-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 3008
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 198
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/498/06498371.pdf
[firstpage_image] =>[orig_patent_app_number] => 09919543
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/919543 | Body-tied-to-body SOI CMOS inverter circuit | Jul 30, 2001 | Issued |
Array
(
[id] => 1321368
[patent_doc_number] => 06605832
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-08-12
[patent_title] => 'Semiconductor structures having reduced contact resistance'
[patent_app_type] => B2
[patent_app_number] => 09/682174
[patent_app_country] => US
[patent_app_date] => 2001-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 3955
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/605/06605832.pdf
[firstpage_image] =>[orig_patent_app_number] => 09682174
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/682174 | Semiconductor structures having reduced contact resistance | Jul 30, 2001 | Issued |
Array
(
[id] => 1534616
[patent_doc_number] => 06489227
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-12-03
[patent_title] => 'Method of etching a polysilicon layer during the stripping of the photoresist shape used as an etch mask to create an opening to an underlying fuse structure'
[patent_app_type] => B1
[patent_app_number] => 09/917303
[patent_app_country] => US
[patent_app_date] => 2001-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 2353
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 222
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/489/06489227.pdf
[firstpage_image] =>[orig_patent_app_number] => 09917303
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/917303 | Method of etching a polysilicon layer during the stripping of the photoresist shape used as an etch mask to create an opening to an underlying fuse structure | Jul 29, 2001 | Issued |
Array
(
[id] => 1545397
[patent_doc_number] => 06444575
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-03
[patent_title] => 'Method for forming a bitline contact via within a memory cell structure'
[patent_app_type] => B1
[patent_app_number] => 09/918084
[patent_app_country] => US
[patent_app_date] => 2001-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 6110
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 177
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/444/06444575.pdf
[firstpage_image] =>[orig_patent_app_number] => 09918084
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/918084 | Method for forming a bitline contact via within a memory cell structure | Jul 29, 2001 | Issued |
Array
(
[id] => 1281012
[patent_doc_number] => 06642112
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-11-04
[patent_title] => 'Non-oxidizing spacer densification method for manufacturing semiconductor devices'
[patent_app_type] => B1
[patent_app_number] => 09/918364
[patent_app_country] => US
[patent_app_date] => 2001-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 6608
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/642/06642112.pdf
[firstpage_image] =>[orig_patent_app_number] => 09918364
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/918364 | Non-oxidizing spacer densification method for manufacturing semiconductor devices | Jul 29, 2001 | Issued |
Array
(
[id] => 6474280
[patent_doc_number] => 20020022338
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-02-21
[patent_title] => 'Method for forming a trench in a semiconductor substrate'
[patent_app_type] => new
[patent_app_number] => 09/917554
[patent_app_country] => US
[patent_app_date] => 2001-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1367
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0022/20020022338.pdf
[firstpage_image] =>[orig_patent_app_number] => 09917554
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/917554 | Method for forming a trench in a semiconductor substrate | Jul 26, 2001 | Issued |
Array
(
[id] => 1449856
[patent_doc_number] => 06455339
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-24
[patent_title] => 'Method for fabricating protrusion of liquid crystal display'
[patent_app_type] => B1
[patent_app_number] => 09/917044
[patent_app_country] => US
[patent_app_date] => 2001-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 1452
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/455/06455339.pdf
[firstpage_image] =>[orig_patent_app_number] => 09917044
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/917044 | Method for fabricating protrusion of liquid crystal display | Jul 26, 2001 | Issued |
Array
(
[id] => 6617955
[patent_doc_number] => 20020064896
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-05-30
[patent_title] => 'Optical waveguides and methods for making the same'
[patent_app_type] => new
[patent_app_number] => 09/916463
[patent_app_country] => US
[patent_app_date] => 2001-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 38328
[patent_no_of_claims] => 56
[patent_no_of_ind_claims] => 11
[patent_words_short_claim] => 14
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0064/20020064896.pdf
[firstpage_image] =>[orig_patent_app_number] => 09916463
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/916463 | Optical waveguides and methods for making the same | Jul 26, 2001 | Issued |
Array
(
[id] => 6753496
[patent_doc_number] => 20030001272
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-01-02
[patent_title] => 'Method of fabricating interlevel connectors using only one photomask step'
[patent_app_type] => new
[patent_app_number] => 09/917364
[patent_app_country] => US
[patent_app_date] => 2001-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4103
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0001/20030001272.pdf
[firstpage_image] =>[orig_patent_app_number] => 09917364
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/917364 | Method of fabricating interlevel connectors using only one photomask step | Jul 26, 2001 | Issued |
Array
(
[id] => 1300040
[patent_doc_number] => 06627946
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-09-30
[patent_title] => 'Semiconductor memory array of floating gate memory cells with control gates protruding portions'
[patent_app_type] => B2
[patent_app_number] => 09/917023
[patent_app_country] => US
[patent_app_date] => 2001-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 43
[patent_no_of_words] => 11057
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 267
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/627/06627946.pdf
[firstpage_image] =>[orig_patent_app_number] => 09917023
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/917023 | Semiconductor memory array of floating gate memory cells with control gates protruding portions | Jul 25, 2001 | Issued |
Array
(
[id] => 5906754
[patent_doc_number] => 20020142544
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-10-03
[patent_title] => 'Method of forming a self-aligned floating gate poly to an active region for a flash E2PROM cell'
[patent_app_type] => new
[patent_app_number] => 09/916423
[patent_app_country] => US
[patent_app_date] => 2001-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2084
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0142/20020142544.pdf
[firstpage_image] =>[orig_patent_app_number] => 09916423
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/916423 | Self-aligned floating gate poly for a flash E2PROM cell | Jul 25, 2001 | Issued |
Array
(
[id] => 1332407
[patent_doc_number] => 06596610
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-07-22
[patent_title] => 'Method for reclaiming delaminated wafer and reclaimed delaminated wafer'
[patent_app_type] => B1
[patent_app_number] => 09/889933
[patent_app_country] => US
[patent_app_date] => 2001-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 5883
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/596/06596610.pdf
[firstpage_image] =>[orig_patent_app_number] => 09889933
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/889933 | Method for reclaiming delaminated wafer and reclaimed delaminated wafer | Jul 24, 2001 | Issued |
Array
(
[id] => 1400996
[patent_doc_number] => 06534331
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-03-18
[patent_title] => 'Method for making a vertical-cavity surface emitting laser with improved current confinement'
[patent_app_type] => B2
[patent_app_number] => 09/912803
[patent_app_country] => US
[patent_app_date] => 2001-07-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 3484
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/534/06534331.pdf
[firstpage_image] =>[orig_patent_app_number] => 09912803
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/912803 | Method for making a vertical-cavity surface emitting laser with improved current confinement | Jul 23, 2001 | Issued |
Array
(
[id] => 1346831
[patent_doc_number] => 06579734
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-06-17
[patent_title] => 'Wire bonding method'
[patent_app_type] => B2
[patent_app_number] => 09/910953
[patent_app_country] => US
[patent_app_date] => 2001-07-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 15
[patent_no_of_words] => 3136
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/579/06579734.pdf
[firstpage_image] =>[orig_patent_app_number] => 09910953
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/910953 | Wire bonding method | Jul 23, 2001 | Issued |
Array
(
[id] => 6774332
[patent_doc_number] => 20030017670
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-01-23
[patent_title] => 'Method of manufacturing a semiconductor memory device with a gate dielectric stack'
[patent_app_type] => new
[patent_app_number] => 09/908704
[patent_app_country] => US
[patent_app_date] => 2001-07-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2316
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0017/20030017670.pdf
[firstpage_image] =>[orig_patent_app_number] => 09908704
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/908704 | Method of manufacturing a semiconductor memory device with a gate dielectric stack | Jul 19, 2001 | Abandoned |
Array
(
[id] => 1362349
[patent_doc_number] => 06569784
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-05-27
[patent_title] => 'Material of photoresist protect oxide'
[patent_app_type] => B1
[patent_app_number] => 09/908823
[patent_app_country] => US
[patent_app_date] => 2001-07-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 2664
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/569/06569784.pdf
[firstpage_image] =>[orig_patent_app_number] => 09908823
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/908823 | Material of photoresist protect oxide | Jul 19, 2001 | Issued |
Array
(
[id] => 1290953
[patent_doc_number] => 06630366
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-10-07
[patent_title] => 'Manufacturing method for light emitting device'
[patent_app_type] => B2
[patent_app_number] => 09/909254
[patent_app_country] => US
[patent_app_date] => 2001-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 27
[patent_no_of_words] => 6698
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/630/06630366.pdf
[firstpage_image] =>[orig_patent_app_number] => 09909254
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/909254 | Manufacturing method for light emitting device | Jul 18, 2001 | Issued |
Array
(
[id] => 6342701
[patent_doc_number] => 20020034837
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-03-21
[patent_title] => 'Method of activating CdTe thin-film solar cells'
[patent_app_type] => new
[patent_app_number] => 09/908384
[patent_app_country] => US
[patent_app_date] => 2001-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2581
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0034/20020034837.pdf
[firstpage_image] =>[orig_patent_app_number] => 09908384
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/908384 | Method of activating CdTe thin-film solar cells | Jul 17, 2001 | Abandoned |
Array
(
[id] => 1534627
[patent_doc_number] => 06489231
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-12-03
[patent_title] => 'Method for forming barrier and seed layer'
[patent_app_type] => B1
[patent_app_number] => 09/907424
[patent_app_country] => US
[patent_app_date] => 2001-07-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 7
[patent_no_of_words] => 3101
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/489/06489231.pdf
[firstpage_image] =>[orig_patent_app_number] => 09907424
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/907424 | Method for forming barrier and seed layer | Jul 16, 2001 | Issued |
Array
(
[id] => 5870762
[patent_doc_number] => 20020047218
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-04-25
[patent_title] => 'Bond pad of semiconductor device and method of fabricating the same'
[patent_app_type] => new
[patent_app_number] => 09/906303
[patent_app_country] => US
[patent_app_date] => 2001-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5355
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0047/20020047218.pdf
[firstpage_image] =>[orig_patent_app_number] => 09906303
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/906303 | Bond pad of semiconductor device and method of fabricating the same | Jul 15, 2001 | Issued |