Search

Long Pham

Examiner (ID: 5269, Phone: (571)272-1714 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2822, 2899, 2897, 2823, 1107, 2814, 2812, 1763
Total Applications
3774
Issued Applications
3306
Pending Applications
160
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1385346 [patent_doc_number] => 06548333 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-15 [patent_title] => 'Aluminum gallium nitride/gallium nitride high electron mobility transistors having a gate contact on a gallium nitride based cap segment' [patent_app_type] => B2 [patent_app_number] => 09/904333 [patent_app_country] => US [patent_app_date] => 2001-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4655 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/548/06548333.pdf [firstpage_image] =>[orig_patent_app_number] => 09904333 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/904333
Aluminum gallium nitride/gallium nitride high electron mobility transistors having a gate contact on a gallium nitride based cap segment Jul 11, 2001 Issued
Array ( [id] => 1212702 [patent_doc_number] => 06709920 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-23 [patent_title] => 'Method of fabricating a non-volatile memory device having a tunnel-insulating layer including more than two portions of different thickness' [patent_app_type] => B2 [patent_app_number] => 09/902243 [patent_app_country] => US [patent_app_date] => 2001-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2558 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/709/06709920.pdf [firstpage_image] =>[orig_patent_app_number] => 09902243 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/902243
Method of fabricating a non-volatile memory device having a tunnel-insulating layer including more than two portions of different thickness Jul 9, 2001 Issued
Array ( [id] => 5951483 [patent_doc_number] => 20020006709 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-17 [patent_title] => 'Process for producing semiconductor device' [patent_app_type] => new [patent_app_number] => 09/900453 [patent_app_country] => US [patent_app_date] => 2001-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5954 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20020006709.pdf [firstpage_image] =>[orig_patent_app_number] => 09900453 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/900453
Process for producing semiconductor device Jul 8, 2001 Issued
Array ( [id] => 6651389 [patent_doc_number] => 20030008495 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-09 [patent_title] => 'Selective barrier metal fabricated for interconnect structure manufacturing process' [patent_app_type] => new [patent_app_number] => 09/897134 [patent_app_country] => US [patent_app_date] => 2001-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2349 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20030008495.pdf [firstpage_image] =>[orig_patent_app_number] => 09897134 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/897134
Selective barrier metal fabricated for interconnect structure manufacturing process Jul 2, 2001 Abandoned
Array ( [id] => 1602587 [patent_doc_number] => 06432766 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Method of fabricating a SRAM device' [patent_app_type] => B1 [patent_app_number] => 09/895874 [patent_app_country] => US [patent_app_date] => 2001-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2069 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/432/06432766.pdf [firstpage_image] =>[orig_patent_app_number] => 09895874 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/895874
Method of fabricating a SRAM device Jul 1, 2001 Issued
Array ( [id] => 6224573 [patent_doc_number] => 20020004249 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-10 [patent_title] => 'Semiconductor memory device and manufacturing method thereof' [patent_app_type] => new [patent_app_number] => 09/893664 [patent_app_country] => US [patent_app_date] => 2001-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11553 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20020004249.pdf [firstpage_image] =>[orig_patent_app_number] => 09893664 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/893664
Semiconductor memory device and manufacturing method thereof Jun 28, 2001 Issued
Array ( [id] => 6290317 [patent_doc_number] => 20020055200 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-09 [patent_title] => 'Process of mounting elements and optical transmission apparatus' [patent_app_type] => new [patent_app_number] => 09/895824 [patent_app_country] => US [patent_app_date] => 2001-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5203 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20020055200.pdf [firstpage_image] =>[orig_patent_app_number] => 09895824 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/895824
Process for mounting device and optical transmission apparatus Jun 28, 2001 Issued
Array ( [id] => 1106237 [patent_doc_number] => 06812542 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-02 [patent_title] => 'Electric fuse whose dielectric breakdown resistance is controlled by injecting impurities into an insulating film of a capacitor structure, and a method for manufacturing the same' [patent_app_type] => B2 [patent_app_number] => 09/892713 [patent_app_country] => US [patent_app_date] => 2001-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 26 [patent_no_of_words] => 7420 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/812/06812542.pdf [firstpage_image] =>[orig_patent_app_number] => 09892713 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/892713
Electric fuse whose dielectric breakdown resistance is controlled by injecting impurities into an insulating film of a capacitor structure, and a method for manufacturing the same Jun 27, 2001 Issued
Array ( [id] => 1393029 [patent_doc_number] => 06541286 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-01 [patent_title] => 'Imaging of integrated circuit interconnects' [patent_app_type] => B1 [patent_app_number] => 09/894284 [patent_app_country] => US [patent_app_date] => 2001-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2957 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/541/06541286.pdf [firstpage_image] =>[orig_patent_app_number] => 09894284 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/894284
Imaging of integrated circuit interconnects Jun 26, 2001 Issued
Array ( [id] => 6224759 [patent_doc_number] => 20020004313 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-10 [patent_title] => 'Method for manufacturing gate structure for use in semiconductor device' [patent_app_type] => new [patent_app_number] => 09/891503 [patent_app_country] => US [patent_app_date] => 2001-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1897 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20020004313.pdf [firstpage_image] =>[orig_patent_app_number] => 09891503 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/891503
Method for manufacturing gate structure for use in semiconductor device Jun 26, 2001 Issued
Array ( [id] => 6327221 [patent_doc_number] => 20020197780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-26 [patent_title] => 'Method for forming a metal oxide semiconductor type field effect transistor' [patent_app_type] => new [patent_app_number] => 09/888494 [patent_app_country] => US [patent_app_date] => 2001-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2290 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20020197780.pdf [firstpage_image] =>[orig_patent_app_number] => 09888494 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/888494
Method for forming a metal oxide semiconductor type field effect transistor Jun 25, 2001 Abandoned
Array ( [id] => 6320093 [patent_doc_number] => 20020196385 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-26 [patent_title] => 'Backlight units for liquid crystal displays' [patent_app_type] => new [patent_app_number] => 09/885742 [patent_app_country] => US [patent_app_date] => 2001-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4957 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0196/20020196385.pdf [firstpage_image] =>[orig_patent_app_number] => 09885742 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/885742
Backlight units for liquid crystal displays Jun 19, 2001 Issued
Array ( [id] => 1358628 [patent_doc_number] => 06573151 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-03 [patent_title] => 'Method of forming zero marks' [patent_app_type] => B1 [patent_app_number] => 09/884204 [patent_app_country] => US [patent_app_date] => 2001-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1689 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/573/06573151.pdf [firstpage_image] =>[orig_patent_app_number] => 09884204 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/884204
Method of forming zero marks Jun 18, 2001 Issued
Array ( [id] => 6880238 [patent_doc_number] => 20010031525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-18 [patent_title] => 'Bipolar-CMOS (BiCMOS) process for fabricating integrated circuits' [patent_app_type] => new [patent_app_number] => 09/873808 [patent_app_country] => US [patent_app_date] => 2001-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3962 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20010031525.pdf [firstpage_image] =>[orig_patent_app_number] => 09873808 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/873808
Bipolar-CMOS (BiCMOS) process for fabricating integrated circuits Jun 3, 2001 Issued
Array ( [id] => 1435892 [patent_doc_number] => 06355535 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-03-12 [patent_title] => 'Method and structure of manufacturing a high-Q inductor with an air trench' [patent_app_type] => B2 [patent_app_number] => 09/873133 [patent_app_country] => US [patent_app_date] => 2001-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 3220 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/355/06355535.pdf [firstpage_image] =>[orig_patent_app_number] => 09873133 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/873133
Method and structure of manufacturing a high-Q inductor with an air trench May 31, 2001 Issued
Array ( [id] => 6407223 [patent_doc_number] => 20020182753 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-05 [patent_title] => 'Method of forming a capacitor in a FeRAM' [patent_app_type] => new [patent_app_number] => 09/865564 [patent_app_country] => US [patent_app_date] => 2001-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2564 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20020182753.pdf [firstpage_image] =>[orig_patent_app_number] => 09865564 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/865564
Method of forming a capacitor in a FeRAM May 28, 2001 Abandoned
Array ( [id] => 6738208 [patent_doc_number] => 20030155576 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-21 [patent_title] => 'Luminescent diode' [patent_app_type] => new [patent_app_number] => 10/332259 [patent_app_country] => US [patent_app_date] => 2003-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1495 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20030155576.pdf [firstpage_image] =>[orig_patent_app_number] => 10332259 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/332259
Luminescent diode May 17, 2001 Issued
Array ( [id] => 6998427 [patent_doc_number] => 20010052611 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-20 [patent_title] => 'Merged memory and logic semiconductor device of salicided dual gate structure including embedded memory of self-aligned contact structure and manufacturing method thereof' [patent_app_type] => new [patent_app_number] => 09/850143 [patent_app_country] => US [patent_app_date] => 2001-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7194 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20010052611.pdf [firstpage_image] =>[orig_patent_app_number] => 09850143 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/850143
Merged memory and logic semiconductor device of salicided dual gate structure including embedded memory of self-aligned contact structure and manufacturing method thereof May 7, 2001 Issued
Array ( [id] => 6896206 [patent_doc_number] => 20010026996 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-04 [patent_title] => 'Semiconductor device and process for producing the sme' [patent_app_type] => new [patent_app_number] => 09/845338 [patent_app_country] => US [patent_app_date] => 2001-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 40 [patent_no_of_words] => 19064 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20010026996.pdf [firstpage_image] =>[orig_patent_app_number] => 09845338 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/845338
Semiconductor device and process for producing the sme Apr 30, 2001 Issued
Array ( [id] => 7634785 [patent_doc_number] => 06656833 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-02 [patent_title] => 'Method of DRAM' [patent_app_type] => B2 [patent_app_number] => 09/842944 [patent_app_country] => US [patent_app_date] => 2001-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 3728 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 12 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/656/06656833.pdf [firstpage_image] =>[orig_patent_app_number] => 09842944 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/842944
Method of DRAM Apr 25, 2001 Issued
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