
Long Pham
Examiner (ID: 5269, Phone: (571)272-1714 , Office: P/2814 )
| Most Active Art Unit | 2814 |
| Art Unit(s) | 2822, 2899, 2897, 2823, 1107, 2814, 2812, 1763 |
| Total Applications | 3774 |
| Issued Applications | 3306 |
| Pending Applications | 160 |
| Abandoned Applications | 335 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1346140
[patent_doc_number] => 06583010
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-06-24
[patent_title] => 'Trench transistor with self-aligned source'
[patent_app_type] => B2
[patent_app_number] => 09/839523
[patent_app_country] => US
[patent_app_date] => 2001-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 4245
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/583/06583010.pdf
[firstpage_image] =>[orig_patent_app_number] => 09839523
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/839523 | Trench transistor with self-aligned source | Apr 19, 2001 | Issued |
Array
(
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[patent_doc_number] => 20020048829
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-04-25
[patent_title] => 'Light emitting device and fabricating method thereof'
[patent_app_type] => new
[patent_app_number] => 09/837324
[patent_app_country] => US
[patent_app_date] => 2001-04-19
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[patent_drawing_sheets_cnt] => 20
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[pdf_file] => publications/A1/0048/20020048829.pdf
[firstpage_image] =>[orig_patent_app_number] => 09837324
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/837324 | Light emitting device and fabricating method thereof | Apr 18, 2001 | Issued |
Array
(
[id] => 1585402
[patent_doc_number] => 06358787
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-03-19
[patent_title] => 'Method of forming CMOS integrated circuitry'
[patent_app_type] => B2
[patent_app_number] => 09/832447
[patent_app_country] => US
[patent_app_date] => 2001-04-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/832447 | Method of forming CMOS integrated circuitry | Apr 9, 2001 | Issued |
Array
(
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[patent_issue_date] => 2002-05-14
[patent_title] => 'Method for making semiconductor device having bent gate electrode'
[patent_app_type] => B2
[patent_app_number] => 09/828873
[patent_app_country] => US
[patent_app_date] => 2001-04-10
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/387/06387760.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/828873 | Method for making semiconductor device having bent gate electrode | Apr 9, 2001 | Issued |
Array
(
[id] => 1315401
[patent_doc_number] => 06607950
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[patent_issue_date] => 2003-08-19
[patent_title] => 'MIS transistors with a metal gate and high-k dielectric and method of forming'
[patent_app_type] => B2
[patent_app_number] => 09/823893
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[patent_drawing_sheets_cnt] => 10
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[pdf_file] => patents/06/607/06607950.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/823893 | MIS transistors with a metal gate and high-k dielectric and method of forming | Mar 29, 2001 | Issued |
Array
(
[id] => 7647067
[patent_doc_number] => 06476451
[patent_country] => US
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[patent_issue_date] => 2002-11-05
[patent_title] => 'Buried guard rings for CMOS device'
[patent_app_type] => B2
[patent_app_number] => 09/811544
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/811544 | Buried guard rings for CMOS device | Mar 19, 2001 | Issued |
Array
(
[id] => 5842637
[patent_doc_number] => 20020131463
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[patent_issue_date] => 2002-09-19
[patent_title] => 'Interband cascade light emitting device and method of making same'
[patent_app_type] => new
[patent_app_number] => 09/805724
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[patent_app_date] => 2001-03-14
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0131/20020131463.pdf
[firstpage_image] =>[orig_patent_app_number] => 09805724
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/805724 | Interband cascade light emitting device and method of making same | Mar 13, 2001 | Issued |
Array
(
[id] => 1300173
[patent_doc_number] => 06627972
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-09-30
[patent_title] => 'Vertical bipolar transistor'
[patent_app_type] => B1
[patent_app_number] => 09/786653
[patent_app_country] => US
[patent_app_date] => 2001-03-07
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/627/06627972.pdf
[firstpage_image] =>[orig_patent_app_number] => 09786653
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/786653 | Vertical bipolar transistor | Mar 6, 2001 | Issued |
Array
(
[id] => 1418032
[patent_doc_number] => 06514816
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-02-04
[patent_title] => 'Method of fabricating a self-aligned shallow trench isolation'
[patent_app_type] => B2
[patent_app_number] => 09/797233
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[patent_app_date] => 2001-03-01
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[pdf_file] => patents/06/514/06514816.pdf
[firstpage_image] =>[orig_patent_app_number] => 09797233
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/797233 | Method of fabricating a self-aligned shallow trench isolation | Feb 28, 2001 | Issued |
Array
(
[id] => 5859352
[patent_doc_number] => 20020123222
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[patent_issue_date] => 2002-09-05
[patent_title] => 'Method of fabricating a salicide layer'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/795143 | Method of fabricating a salicide layer | Feb 28, 2001 | Abandoned |
Array
(
[id] => 1532608
[patent_doc_number] => 06410429
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-06-25
[patent_title] => 'Method for fabricating void-free epitaxial-CoSi2 with ultra-shallow junctions'
[patent_app_type] => B1
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/795113 | Method for fabricating void-free epitaxial-CoSi2 with ultra-shallow junctions | Feb 28, 2001 | Issued |
Array
(
[id] => 7000492
[patent_doc_number] => 20010053561
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[patent_title] => 'Insulated-gate semiconductor element and method for manufacturing the same'
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Array
(
[id] => 1478076
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[patent_title] => 'CMOS inverter configured from double gate MOSFET and method of fabricating same'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/796283 | CMOS inverter configured from double gate MOSFET and method of fabricating same | Feb 27, 2001 | Issued |
Array
(
[id] => 6900114
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/791763 | Production method for shallow trench insulation | Feb 25, 2001 | Issued |
Array
(
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[patent_title] => 'Method of fabrication of semiconductor-on-insulator (SOI) wafer having a Si/SiGe/Si active layer'
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Array
(
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Array
(
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Array
(
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Array
(
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