Search

Long Pham

Examiner (ID: 5269, Phone: (571)272-1714 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2822, 2899, 2897, 2823, 1107, 2814, 2812, 1763
Total Applications
3774
Issued Applications
3306
Pending Applications
160
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1346140 [patent_doc_number] => 06583010 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-24 [patent_title] => 'Trench transistor with self-aligned source' [patent_app_type] => B2 [patent_app_number] => 09/839523 [patent_app_country] => US [patent_app_date] => 2001-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4245 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/583/06583010.pdf [firstpage_image] =>[orig_patent_app_number] => 09839523 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/839523
Trench transistor with self-aligned source Apr 19, 2001 Issued
Array ( [id] => 5873985 [patent_doc_number] => 20020048829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-25 [patent_title] => 'Light emitting device and fabricating method thereof' [patent_app_type] => new [patent_app_number] => 09/837324 [patent_app_country] => US [patent_app_date] => 2001-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 17437 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20020048829.pdf [firstpage_image] =>[orig_patent_app_number] => 09837324 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/837324
Light emitting device and fabricating method thereof Apr 18, 2001 Issued
Array ( [id] => 1585402 [patent_doc_number] => 06358787 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-03-19 [patent_title] => 'Method of forming CMOS integrated circuitry' [patent_app_type] => B2 [patent_app_number] => 09/832447 [patent_app_country] => US [patent_app_date] => 2001-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2591 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/358/06358787.pdf [firstpage_image] =>[orig_patent_app_number] => 09832447 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/832447
Method of forming CMOS integrated circuitry Apr 9, 2001 Issued
Array ( [id] => 1474518 [patent_doc_number] => 06387760 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-05-14 [patent_title] => 'Method for making semiconductor device having bent gate electrode' [patent_app_type] => B2 [patent_app_number] => 09/828873 [patent_app_country] => US [patent_app_date] => 2001-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 2268 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/387/06387760.pdf [firstpage_image] =>[orig_patent_app_number] => 09828873 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/828873
Method for making semiconductor device having bent gate electrode Apr 9, 2001 Issued
Array ( [id] => 1315401 [patent_doc_number] => 06607950 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-08-19 [patent_title] => 'MIS transistors with a metal gate and high-k dielectric and method of forming' [patent_app_type] => B2 [patent_app_number] => 09/823893 [patent_app_country] => US [patent_app_date] => 2001-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 28 [patent_no_of_words] => 7014 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/607/06607950.pdf [firstpage_image] =>[orig_patent_app_number] => 09823893 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/823893
MIS transistors with a metal gate and high-k dielectric and method of forming Mar 29, 2001 Issued
Array ( [id] => 7647067 [patent_doc_number] => 06476451 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-05 [patent_title] => 'Buried guard rings for CMOS device' [patent_app_type] => B2 [patent_app_number] => 09/811544 [patent_app_country] => US [patent_app_date] => 2001-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3124 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 7 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/476/06476451.pdf [firstpage_image] =>[orig_patent_app_number] => 09811544 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/811544
Buried guard rings for CMOS device Mar 19, 2001 Issued
Array ( [id] => 5842637 [patent_doc_number] => 20020131463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-19 [patent_title] => 'Interband cascade light emitting device and method of making same' [patent_app_type] => new [patent_app_number] => 09/805724 [patent_app_country] => US [patent_app_date] => 2001-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5707 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20020131463.pdf [firstpage_image] =>[orig_patent_app_number] => 09805724 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/805724
Interband cascade light emitting device and method of making same Mar 13, 2001 Issued
Array ( [id] => 1300173 [patent_doc_number] => 06627972 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-30 [patent_title] => 'Vertical bipolar transistor' [patent_app_type] => B1 [patent_app_number] => 09/786653 [patent_app_country] => US [patent_app_date] => 2001-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2400 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/627/06627972.pdf [firstpage_image] =>[orig_patent_app_number] => 09786653 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/786653
Vertical bipolar transistor Mar 6, 2001 Issued
Array ( [id] => 1418032 [patent_doc_number] => 06514816 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-02-04 [patent_title] => 'Method of fabricating a self-aligned shallow trench isolation' [patent_app_type] => B2 [patent_app_number] => 09/797233 [patent_app_country] => US [patent_app_date] => 2001-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2564 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 299 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/514/06514816.pdf [firstpage_image] =>[orig_patent_app_number] => 09797233 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/797233
Method of fabricating a self-aligned shallow trench isolation Feb 28, 2001 Issued
Array ( [id] => 5859352 [patent_doc_number] => 20020123222 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-05 [patent_title] => 'Method of fabricating a salicide layer' [patent_app_type] => new [patent_app_number] => 09/795143 [patent_app_country] => US [patent_app_date] => 2001-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1879 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0123/20020123222.pdf [firstpage_image] =>[orig_patent_app_number] => 09795143 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/795143
Method of fabricating a salicide layer Feb 28, 2001 Abandoned
Array ( [id] => 1532608 [patent_doc_number] => 06410429 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-25 [patent_title] => 'Method for fabricating void-free epitaxial-CoSi2 with ultra-shallow junctions' [patent_app_type] => B1 [patent_app_number] => 09/795113 [patent_app_country] => US [patent_app_date] => 2001-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2891 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/410/06410429.pdf [firstpage_image] =>[orig_patent_app_number] => 09795113 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/795113
Method for fabricating void-free epitaxial-CoSi2 with ultra-shallow junctions Feb 28, 2001 Issued
Array ( [id] => 7000492 [patent_doc_number] => 20010053561 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-20 [patent_title] => 'Insulated-gate semiconductor element and method for manufacturing the same' [patent_app_type] => new [patent_app_number] => 09/797466 [patent_app_country] => US [patent_app_date] => 2001-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4968 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20010053561.pdf [firstpage_image] =>[orig_patent_app_number] => 09797466 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/797466
Insulated-gate semiconductor element and method for manufacturing the same Feb 28, 2001 Abandoned
Array ( [id] => 1478076 [patent_doc_number] => 06451656 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'CMOS inverter configured from double gate MOSFET and method of fabricating same' [patent_app_type] => B1 [patent_app_number] => 09/796283 [patent_app_country] => US [patent_app_date] => 2001-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 15 [patent_no_of_words] => 3277 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/451/06451656.pdf [firstpage_image] =>[orig_patent_app_number] => 09796283 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/796283
CMOS inverter configured from double gate MOSFET and method of fabricating same Feb 27, 2001 Issued
Array ( [id] => 6900114 [patent_doc_number] => 20010009790 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-07-26 [patent_title] => 'Self-aligned lateral DMOS with spacer drift region' [patent_app_type] => new [patent_app_number] => 09/796384 [patent_app_country] => US [patent_app_date] => 2001-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2099 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0009/20010009790.pdf [firstpage_image] =>[orig_patent_app_number] => 09796384 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/796384
Method of forming Self-aligned lateral DMOS with spacer drift region Feb 27, 2001 Issued
Array ( [id] => 6897455 [patent_doc_number] => 20010045620 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-29 [patent_title] => 'Semiconductor device and production method thereof' [patent_app_type] => new [patent_app_number] => 09/791763 [patent_app_country] => US [patent_app_date] => 2001-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5174 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20010045620.pdf [firstpage_image] =>[orig_patent_app_number] => 09791763 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/791763
Production method for shallow trench insulation Feb 25, 2001 Issued
Array ( [id] => 1532388 [patent_doc_number] => 06410371 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-25 [patent_title] => 'Method of fabrication of semiconductor-on-insulator (SOI) wafer having a Si/SiGe/Si active layer' [patent_app_type] => B1 [patent_app_number] => 09/794884 [patent_app_country] => US [patent_app_date] => 2001-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2351 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/410/06410371.pdf [firstpage_image] =>[orig_patent_app_number] => 09794884 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/794884
Method of fabrication of semiconductor-on-insulator (SOI) wafer having a Si/SiGe/Si active layer Feb 25, 2001 Issued
Array ( [id] => 1458811 [patent_doc_number] => 06426271 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-07-30 [patent_title] => 'Method of rounding the corner of a shallow trench isolation region' [patent_app_type] => B2 [patent_app_number] => 09/790493 [patent_app_country] => US [patent_app_date] => 2001-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2812 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/426/06426271.pdf [firstpage_image] =>[orig_patent_app_number] => 09790493 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/790493
Method of rounding the corner of a shallow trench isolation region Feb 22, 2001 Issued
Array ( [id] => 6435377 [patent_doc_number] => 20020127863 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-12 [patent_title] => 'Method of fabricating recessed locos isolation for semiconductor device' [patent_app_type] => new [patent_app_number] => 09/791314 [patent_app_country] => US [patent_app_date] => 2001-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1860 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20020127863.pdf [firstpage_image] =>[orig_patent_app_number] => 09791314 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/791314
Method of fabricating recessed locos isolation for semiconductor device Feb 21, 2001 Abandoned
Array ( [id] => 5922080 [patent_doc_number] => 20020115288 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-22 [patent_title] => 'Method for decreasing the resistivity of the gate and the leaky junction of the source/drain' [patent_app_type] => new [patent_app_number] => 09/790163 [patent_app_country] => US [patent_app_date] => 2001-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2629 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20020115288.pdf [firstpage_image] =>[orig_patent_app_number] => 09790163 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/790163
Method for decreasing the resistivity of the gate and the leaky junction of the source/drain Feb 20, 2001 Issued
Array ( [id] => 5922090 [patent_doc_number] => 20020115289 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-22 [patent_title] => 'METHOD FOR DECREASING THE RESISTIVITY OF THE GATE AND THE LEAKY JUNCTION OF THE SOURCE/DRAIN' [patent_app_type] => new [patent_app_number] => 09/790164 [patent_app_country] => US [patent_app_date] => 2001-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2514 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20020115289.pdf [firstpage_image] =>[orig_patent_app_number] => 09790164 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/790164
METHOD FOR DECREASING THE RESISTIVITY OF THE GATE AND THE LEAKY JUNCTION OF THE SOURCE/DRAIN Feb 20, 2001 Abandoned
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