
Long Pham
Examiner (ID: 5269, Phone: (571)272-1714 , Office: P/2814 )
| Most Active Art Unit | 2814 |
| Art Unit(s) | 2822, 2899, 2897, 2823, 1107, 2814, 2812, 1763 |
| Total Applications | 3774 |
| Issued Applications | 3306 |
| Pending Applications | 160 |
| Abandoned Applications | 335 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7076898
[patent_doc_number] => 20010040246
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-11-15
[patent_title] => 'GaN field-effect transistor and method of manufacturing the same'
[patent_app_type] => new
[patent_app_number] => 09/784833
[patent_app_country] => US
[patent_app_date] => 2001-02-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
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[pdf_file] => publications/A1/0040/20010040246.pdf
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Array
(
[id] => 1095977
[patent_doc_number] => 06821852
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[patent_kind] => B2
[patent_issue_date] => 2004-11-23
[patent_title] => 'Dual doped gates'
[patent_app_type] => B2
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/782743 | Dual doped gates | Feb 12, 2001 | Issued |
Array
(
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[patent_doc_number] => 06395589
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[patent_issue_date] => 2002-05-28
[patent_title] => 'Fabrication of fully depleted field effect transistor with high-K gate dielectric in SOI technology'
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[patent_app_number] => 09/781783
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Array
(
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[patent_issue_date] => 2002-06-18
[patent_title] => 'Fabrication of fully depleted field effect transistor with raised source and drain in SOI technology'
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[patent_app_number] => 09/781364
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Array
(
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[patent_issue_date] => 2002-09-17
[patent_title] => 'Transistor with an ultra short channel length defined by a laterally diffused nitrogen implant'
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Array
(
[id] => 7640306
[patent_doc_number] => 06395608
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[patent_issue_date] => 2002-05-28
[patent_title] => 'Heterojunction bipolar transistor and its fabrication method'
[patent_app_type] => B2
[patent_app_number] => 09/770503
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Array
(
[id] => 6503556
[patent_doc_number] => 20020025673
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[patent_issue_date] => 2002-02-28
[patent_title] => 'Method for forming gate by using Co-silicide'
[patent_app_type] => new
[patent_app_number] => 09/737803
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/737803 | Method for forming gate by using Co-silicide | Dec 17, 2000 | Abandoned |
Array
(
[id] => 1409800
[patent_doc_number] => 06528401
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[patent_kind] => B2
[patent_issue_date] => 2003-03-04
[patent_title] => 'Method for fabricating polycide dual gate in semiconductor device'
[patent_app_type] => B2
[patent_app_number] => 09/735544
[patent_app_country] => US
[patent_app_date] => 2000-12-14
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/735544 | Method for fabricating polycide dual gate in semiconductor device | Dec 13, 2000 | Issued |
Array
(
[id] => 7645710
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/701633 | Method of manufacturing semiconductor device | Nov 30, 2000 | Issued |
Array
(
[id] => 1104996
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[patent_title] => 'Method and interlevel dielectric structure for improved metal step coverage'
[patent_app_type] => B1
[patent_app_number] => 09/712827
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Array
(
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Array
(
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Array
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Array
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Array
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Array
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Array
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/667953 | Cathode contact structures in organic electroluminescent devices | Sep 21, 2000 | Issued |