Search

Long Pham

Examiner (ID: 5269, Phone: (571)272-1714 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2822, 2899, 2897, 2823, 1107, 2814, 2812, 1763
Total Applications
3774
Issued Applications
3306
Pending Applications
160
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7076898 [patent_doc_number] => 20010040246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-15 [patent_title] => 'GaN field-effect transistor and method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 09/784833 [patent_app_country] => US [patent_app_date] => 2001-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9354 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20010040246.pdf [firstpage_image] =>[orig_patent_app_number] => 09784833 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/784833
GaN field-effect transistor and method of manufacturing the same Feb 15, 2001 Abandoned
Array ( [id] => 1095977 [patent_doc_number] => 06821852 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-23 [patent_title] => 'Dual doped gates' [patent_app_type] => B2 [patent_app_number] => 09/782743 [patent_app_country] => US [patent_app_date] => 2001-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 26 [patent_no_of_words] => 7815 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/821/06821852.pdf [firstpage_image] =>[orig_patent_app_number] => 09782743 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/782743
Dual doped gates Feb 12, 2001 Issued
Array ( [id] => 7640325 [patent_doc_number] => 06395589 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Fabrication of fully depleted field effect transistor with high-K gate dielectric in SOI technology' [patent_app_type] => B1 [patent_app_number] => 09/781783 [patent_app_country] => US [patent_app_date] => 2001-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 4121 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/395/06395589.pdf [firstpage_image] =>[orig_patent_app_number] => 09781783 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/781783
Fabrication of fully depleted field effect transistor with high-K gate dielectric in SOI technology Feb 11, 2001 Issued
Array ( [id] => 1469763 [patent_doc_number] => 06406951 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-18 [patent_title] => 'Fabrication of fully depleted field effect transistor with raised source and drain in SOI technology' [patent_app_type] => B1 [patent_app_number] => 09/781364 [patent_app_country] => US [patent_app_date] => 2001-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 3344 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 330 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/406/06406951.pdf [firstpage_image] =>[orig_patent_app_number] => 09781364 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/781364
Fabrication of fully depleted field effect transistor with raised source and drain in SOI technology Feb 11, 2001 Issued
Array ( [id] => 1478079 [patent_doc_number] => 06451657 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'Transistor with an ultra short channel length defined by a laterally diffused nitrogen implant' [patent_app_type] => B1 [patent_app_number] => 09/781044 [patent_app_country] => US [patent_app_date] => 2001-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 5257 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/451/06451657.pdf [firstpage_image] =>[orig_patent_app_number] => 09781044 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/781044
Transistor with an ultra short channel length defined by a laterally diffused nitrogen implant Feb 7, 2001 Issued
Array ( [id] => 7640306 [patent_doc_number] => 06395608 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-05-28 [patent_title] => 'Heterojunction bipolar transistor and its fabrication method' [patent_app_type] => B2 [patent_app_number] => 09/770503 [patent_app_country] => US [patent_app_date] => 2001-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 60 [patent_no_of_words] => 6560 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 13 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/395/06395608.pdf [firstpage_image] =>[orig_patent_app_number] => 09770503 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/770503
Heterojunction bipolar transistor and its fabrication method Jan 28, 2001 Issued
Array ( [id] => 6503556 [patent_doc_number] => 20020025673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-28 [patent_title] => 'Method for forming gate by using Co-silicide' [patent_app_type] => new [patent_app_number] => 09/737803 [patent_app_country] => US [patent_app_date] => 2000-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1609 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20020025673.pdf [firstpage_image] =>[orig_patent_app_number] => 09737803 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/737803
Method for forming gate by using Co-silicide Dec 17, 2000 Abandoned
Array ( [id] => 1409800 [patent_doc_number] => 06528401 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-04 [patent_title] => 'Method for fabricating polycide dual gate in semiconductor device' [patent_app_type] => B2 [patent_app_number] => 09/735544 [patent_app_country] => US [patent_app_date] => 2000-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 4310 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/528/06528401.pdf [firstpage_image] =>[orig_patent_app_number] => 09735544 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/735544
Method for fabricating polycide dual gate in semiconductor device Dec 13, 2000 Issued
Array ( [id] => 7645710 [patent_doc_number] => 06472259 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-29 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/701633 [patent_app_country] => US [patent_app_date] => 2000-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 26 [patent_no_of_words] => 5158 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/472/06472259.pdf [firstpage_image] =>[orig_patent_app_number] => 09701633 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/701633
Method of manufacturing semiconductor device Nov 30, 2000 Issued
Array ( [id] => 1104996 [patent_doc_number] => 06812142 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-02 [patent_title] => 'Method and interlevel dielectric structure for improved metal step coverage' [patent_app_type] => B1 [patent_app_number] => 09/712827 [patent_app_country] => US [patent_app_date] => 2000-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2938 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/812/06812142.pdf [firstpage_image] =>[orig_patent_app_number] => 09712827 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/712827
Method and interlevel dielectric structure for improved metal step coverage Nov 13, 2000 Issued
Array ( [id] => 1542502 [patent_doc_number] => 06372559 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Method for self-aligned vertical double-gate MOSFET' [patent_app_type] => B1 [patent_app_number] => 09/709073 [patent_app_country] => US [patent_app_date] => 2000-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3380 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/372/06372559.pdf [firstpage_image] =>[orig_patent_app_number] => 09709073 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/709073
Method for self-aligned vertical double-gate MOSFET Nov 8, 2000 Issued
Array ( [id] => 1335988 [patent_doc_number] => 06593180 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-15 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/708044 [patent_app_country] => US [patent_app_date] => 2000-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 4035 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/593/06593180.pdf [firstpage_image] =>[orig_patent_app_number] => 09708044 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/708044
Method of manufacturing semiconductor device Nov 7, 2000 Issued
Array ( [id] => 1453479 [patent_doc_number] => 06461910 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-08 [patent_title] => 'Method of forming a capacitor in a semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/708063 [patent_app_country] => US [patent_app_date] => 2000-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 1870 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/461/06461910.pdf [firstpage_image] =>[orig_patent_app_number] => 09708063 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/708063
Method of forming a capacitor in a semiconductor device Nov 7, 2000 Issued
Array ( [id] => 1014638 [patent_doc_number] => 06893980 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-17 [patent_title] => 'Semiconductor device and manufacturing method therefor' [patent_app_type] => utility [patent_app_number] => 09/708043 [patent_app_country] => US [patent_app_date] => 2000-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 35 [patent_no_of_words] => 8477 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/893/06893980.pdf [firstpage_image] =>[orig_patent_app_number] => 09708043 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/708043
Semiconductor device and manufacturing method therefor Nov 7, 2000 Issued
Array ( [id] => 1336273 [patent_doc_number] => 06593210 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-15 [patent_title] => 'Self-aligned/maskless reverse etch process using an inorganic film' [patent_app_type] => B1 [patent_app_number] => 09/707214 [patent_app_country] => US [patent_app_date] => 2000-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3093 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/593/06593210.pdf [firstpage_image] =>[orig_patent_app_number] => 09707214 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/707214
Self-aligned/maskless reverse etch process using an inorganic film Nov 5, 2000 Issued
Array ( [id] => 1459522 [patent_doc_number] => 06391764 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Method for fabricating semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/705704 [patent_app_country] => US [patent_app_date] => 2000-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 4174 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/391/06391764.pdf [firstpage_image] =>[orig_patent_app_number] => 09705704 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/705704
Method for fabricating semiconductor device Nov 5, 2000 Issued
Array ( [id] => 895269 [patent_doc_number] => RE040139 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2008-03-04 [patent_title] => 'Wafer having chamfered bend portions in the joint regions between the contour of the cut-away portion of the wafer' [patent_app_type] => reissue [patent_app_number] => 09/704529 [patent_app_country] => US [patent_app_date] => 2000-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 4286 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/040/RE040139.pdf [firstpage_image] =>[orig_patent_app_number] => 09704529 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/704529
Wafer having chamfered bend portions in the joint regions between the contour of the cut-away portion of the wafer Nov 2, 2000 Issued
Array ( [id] => 1327232 [patent_doc_number] => 06599820 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-29 [patent_title] => 'Method of producing a semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/695223 [patent_app_country] => US [patent_app_date] => 2000-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 47 [patent_no_of_words] => 7400 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/599/06599820.pdf [firstpage_image] =>[orig_patent_app_number] => 09695223 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/695223
Method of producing a semiconductor device Oct 24, 2000 Issued
Array ( [id] => 1594538 [patent_doc_number] => 06383912 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Fabrication method of integrated circuits with multiple low dielectric-constant intermetal dielectrics' [patent_app_type] => B1 [patent_app_number] => 09/694194 [patent_app_country] => US [patent_app_date] => 2000-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 7755 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/383/06383912.pdf [firstpage_image] =>[orig_patent_app_number] => 09694194 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/694194
Fabrication method of integrated circuits with multiple low dielectric-constant intermetal dielectrics Oct 22, 2000 Issued
Array ( [id] => 1553399 [patent_doc_number] => 06348359 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-19 [patent_title] => 'Cathode contact structures in organic electroluminescent devices' [patent_app_type] => B1 [patent_app_number] => 09/667953 [patent_app_country] => US [patent_app_date] => 2000-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 5278 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/348/06348359.pdf [firstpage_image] =>[orig_patent_app_number] => 09667953 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/667953
Cathode contact structures in organic electroluminescent devices Sep 21, 2000 Issued
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