Search

Long Pham

Examiner (ID: 5269, Phone: (571)272-1714 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2822, 2899, 2897, 2823, 1107, 2814, 2812, 1763
Total Applications
3774
Issued Applications
3306
Pending Applications
160
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1485269 [patent_doc_number] => 06365479 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Method for independent control of polycrystalline silicon-germanium in a silicon-germanium HBT and related structure' [patent_app_type] => B1 [patent_app_number] => 09/667274 [patent_app_country] => US [patent_app_date] => 2000-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6189 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/365/06365479.pdf [firstpage_image] =>[orig_patent_app_number] => 09667274 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/667274
Method for independent control of polycrystalline silicon-germanium in a silicon-germanium HBT and related structure Sep 21, 2000 Issued
Array ( [id] => 1485160 [patent_doc_number] => 06365449 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Process for making a non-volatile memory cell with a polysilicon spacer defined select gate' [patent_app_type] => B1 [patent_app_number] => 09/657882 [patent_app_country] => US [patent_app_date] => 2000-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2220 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/365/06365449.pdf [firstpage_image] =>[orig_patent_app_number] => 09657882 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/657882
Process for making a non-volatile memory cell with a polysilicon spacer defined select gate Sep 7, 2000 Issued
Array ( [id] => 7643953 [patent_doc_number] => 06429085 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Self-aligned non-selective thin-epi-base silicon germaniun (SiGe) heterojunction bipolar transistor BiCMOS process using silicon dioxide etchback' [patent_app_type] => B1 [patent_app_number] => 09/656117 [patent_app_country] => US [patent_app_date] => 2000-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 2198 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 9 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/429/06429085.pdf [firstpage_image] =>[orig_patent_app_number] => 09656117 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/656117
Self-aligned non-selective thin-epi-base silicon germaniun (SiGe) heterojunction bipolar transistor BiCMOS process using silicon dioxide etchback Sep 5, 2000 Issued
Array ( [id] => 1417652 [patent_doc_number] => 06514784 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Laser-induced bandgap shifting for photonic device integration' [patent_app_type] => B1 [patent_app_number] => 09/654614 [patent_app_country] => US [patent_app_date] => 2000-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2891 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/514/06514784.pdf [firstpage_image] =>[orig_patent_app_number] => 09654614 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/654614
Laser-induced bandgap shifting for photonic device integration Aug 31, 2000 Issued
Array ( [id] => 1517317 [patent_doc_number] => 06500743 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-31 [patent_title] => 'Method of copper-polysilicon T-gate formation' [patent_app_type] => B1 [patent_app_number] => 09/651513 [patent_app_country] => US [patent_app_date] => 2000-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 24 [patent_no_of_words] => 5457 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/500/06500743.pdf [firstpage_image] =>[orig_patent_app_number] => 09651513 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/651513
Method of copper-polysilicon T-gate formation Aug 29, 2000 Issued
Array ( [id] => 1494897 [patent_doc_number] => 06403432 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Hardmask for a salicide gate process with trench isolation' [patent_app_type] => B1 [patent_app_number] => 09/637353 [patent_app_country] => US [patent_app_date] => 2000-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 4100 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/403/06403432.pdf [firstpage_image] =>[orig_patent_app_number] => 09637353 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/637353
Hardmask for a salicide gate process with trench isolation Aug 14, 2000 Issued
Array ( [id] => 1578226 [patent_doc_number] => 06448163 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-10 [patent_title] => 'Method for fabricating T-shaped transistor gate' [patent_app_type] => B1 [patent_app_number] => 09/636273 [patent_app_country] => US [patent_app_date] => 2000-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3199 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/448/06448163.pdf [firstpage_image] =>[orig_patent_app_number] => 09636273 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/636273
Method for fabricating T-shaped transistor gate Aug 9, 2000 Issued
Array ( [id] => 1459542 [patent_doc_number] => 06391772 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Method for forming interconnects in semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/635104 [patent_app_country] => US [patent_app_date] => 2000-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 3793 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/391/06391772.pdf [firstpage_image] =>[orig_patent_app_number] => 09635104 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/635104
Method for forming interconnects in semiconductor device Aug 8, 2000 Issued
Array ( [id] => 1239589 [patent_doc_number] => 06686234 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-03 [patent_title] => 'Semiconductor device and method for fabricating the same' [patent_app_type] => B1 [patent_app_number] => 09/631834 [patent_app_country] => US [patent_app_date] => 2000-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 44 [patent_no_of_words] => 7127 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/686/06686234.pdf [firstpage_image] =>[orig_patent_app_number] => 09631834 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/631834
Semiconductor device and method for fabricating the same Aug 2, 2000 Issued
Array ( [id] => 4408480 [patent_doc_number] => 06309959 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Formation of self-aligned passivation for interconnect to minimize electromigration' [patent_app_type] => 1 [patent_app_number] => 9/630943 [patent_app_country] => US [patent_app_date] => 2000-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 6124 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 316 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/309/06309959.pdf [firstpage_image] =>[orig_patent_app_number] => 630943 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/630943
Formation of self-aligned passivation for interconnect to minimize electromigration Aug 2, 2000 Issued
Array ( [id] => 1398639 [patent_doc_number] => 06537867 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-25 [patent_title] => 'High speed low voltage semiconductor devices and method of fabrication' [patent_app_type] => B1 [patent_app_number] => 09/630463 [patent_app_country] => US [patent_app_date] => 2000-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3032 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/537/06537867.pdf [firstpage_image] =>[orig_patent_app_number] => 09630463 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/630463
High speed low voltage semiconductor devices and method of fabrication Aug 1, 2000 Issued
Array ( [id] => 7636615 [patent_doc_number] => 06380040 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-30 [patent_title] => 'Prevention of dopant out-diffusion during silicidation and junction formation' [patent_app_type] => B1 [patent_app_number] => 09/629883 [patent_app_country] => US [patent_app_date] => 2000-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 4178 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 11 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/380/06380040.pdf [firstpage_image] =>[orig_patent_app_number] => 09629883 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/629883
Prevention of dopant out-diffusion during silicidation and junction formation Jul 31, 2000 Issued
Array ( [id] => 1494915 [patent_doc_number] => 06403439 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Method of preparing for structural analysis a deep trench-type capacitor and method of structural analysis therefor' [patent_app_type] => B1 [patent_app_number] => 09/629733 [patent_app_country] => US [patent_app_date] => 2000-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3013 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/403/06403439.pdf [firstpage_image] =>[orig_patent_app_number] => 09629733 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/629733
Method of preparing for structural analysis a deep trench-type capacitor and method of structural analysis therefor Jul 30, 2000 Issued
Array ( [id] => 1523704 [patent_doc_number] => 06352906 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-05 [patent_title] => 'Nitridization of STI sidewalls' [patent_app_type] => B1 [patent_app_number] => 09/628864 [patent_app_country] => US [patent_app_date] => 2000-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 824 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/352/06352906.pdf [firstpage_image] =>[orig_patent_app_number] => 09628864 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/628864
Nitridization of STI sidewalls Jul 27, 2000 Issued
Array ( [id] => 1494845 [patent_doc_number] => 06403420 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Nitrogen implant after bit-line formation for ONO flash memory devices' [patent_app_type] => B1 [patent_app_number] => 09/627664 [patent_app_country] => US [patent_app_date] => 2000-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 17 [patent_no_of_words] => 1385 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/403/06403420.pdf [firstpage_image] =>[orig_patent_app_number] => 09627664 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/627664
Nitrogen implant after bit-line formation for ONO flash memory devices Jul 27, 2000 Issued
Array ( [id] => 4381228 [patent_doc_number] => 06277709 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Method of forming shallow trench isolation structure' [patent_app_type] => 1 [patent_app_number] => 9/628214 [patent_app_country] => US [patent_app_date] => 2000-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 1959 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/277/06277709.pdf [firstpage_image] =>[orig_patent_app_number] => 628214 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/628214
Method of forming shallow trench isolation structure Jul 27, 2000 Issued
Array ( [id] => 1595499 [patent_doc_number] => 06492227 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'Method for fabricating flash memory device using dual damascene process' [patent_app_type] => B1 [patent_app_number] => 09/624563 [patent_app_country] => US [patent_app_date] => 2000-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 19 [patent_no_of_words] => 5223 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/492/06492227.pdf [firstpage_image] =>[orig_patent_app_number] => 09624563 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/624563
Method for fabricating flash memory device using dual damascene process Jul 23, 2000 Issued
Array ( [id] => 1477671 [patent_doc_number] => 06344395 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-05 [patent_title] => 'Method for implementing non-volatile memory on a semiconductor substrate' [patent_app_type] => B1 [patent_app_number] => 09/624324 [patent_app_country] => US [patent_app_date] => 2000-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 30 [patent_no_of_words] => 4391 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 579 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/344/06344395.pdf [firstpage_image] =>[orig_patent_app_number] => 09624324 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/624324
Method for implementing non-volatile memory on a semiconductor substrate Jul 23, 2000 Issued
Array ( [id] => 1076891 [patent_doc_number] => 07615402 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-11-10 [patent_title] => 'Electrostatically operated tunneling transistor' [patent_app_type] => utility [patent_app_number] => 09/612607 [patent_app_country] => US [patent_app_date] => 2000-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4747 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/615/07615402.pdf [firstpage_image] =>[orig_patent_app_number] => 09612607 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/612607
Electrostatically operated tunneling transistor Jul 6, 2000 Issued
Array ( [id] => 4329498 [patent_doc_number] => 06313029 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'Method for forming multi-layer interconnection of a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/606874 [patent_app_country] => US [patent_app_date] => 2000-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2385 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/313/06313029.pdf [firstpage_image] =>[orig_patent_app_number] => 606874 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/606874
Method for forming multi-layer interconnection of a semiconductor device Jun 27, 2000 Issued
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