Search

Long Pham

Examiner (ID: 5269, Phone: (571)272-1714 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2822, 2899, 2897, 2823, 1107, 2814, 2812, 1763
Total Applications
3774
Issued Applications
3306
Pending Applications
160
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4275500 [patent_doc_number] => 06281085 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/605634 [patent_app_country] => US [patent_app_date] => 2000-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 1685 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/281/06281085.pdf [firstpage_image] =>[orig_patent_app_number] => 605634 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/605634
Method of manufacturing a semiconductor device Jun 27, 2000 Issued
Array ( [id] => 1564994 [patent_doc_number] => 06339017 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-15 [patent_title] => 'Hard mask for integrated circuit fabrication' [patent_app_type] => B1 [patent_app_number] => 09/596993 [patent_app_country] => US [patent_app_date] => 2000-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 4022 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/339/06339017.pdf [firstpage_image] =>[orig_patent_app_number] => 09596993 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/596993
Hard mask for integrated circuit fabrication Jun 19, 2000 Issued
Array ( [id] => 732648 [patent_doc_number] => 07037796 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-05-02 [patent_title] => 'Method of manufacturing spacers on sidewalls of titanium polycide gate' [patent_app_type] => utility [patent_app_number] => 09/598673 [patent_app_country] => US [patent_app_date] => 2000-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 1737 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/037/07037796.pdf [firstpage_image] =>[orig_patent_app_number] => 09598673 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/598673
Method of manufacturing spacers on sidewalls of titanium polycide gate Jun 19, 2000 Issued
Array ( [id] => 1459481 [patent_doc_number] => 06391753 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Process for forming gate conductors' [patent_app_type] => B1 [patent_app_number] => 09/597624 [patent_app_country] => US [patent_app_date] => 2000-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 3047 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/391/06391753.pdf [firstpage_image] =>[orig_patent_app_number] => 09597624 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/597624
Process for forming gate conductors Jun 19, 2000 Issued
Array ( [id] => 7636634 [patent_doc_number] => 06380021 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-30 [patent_title] => 'Ultra-shallow junction formation by novel process sequence for PMOSFET' [patent_app_type] => B1 [patent_app_number] => 09/597193 [patent_app_country] => US [patent_app_date] => 2000-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2283 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 10 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/380/06380021.pdf [firstpage_image] =>[orig_patent_app_number] => 09597193 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/597193
Ultra-shallow junction formation by novel process sequence for PMOSFET Jun 19, 2000 Issued
Array ( [id] => 1585600 [patent_doc_number] => 06358836 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Wafer level package incorporating elastomeric pads in dummy plugs' [patent_app_type] => B1 [patent_app_number] => 09/595823 [patent_app_country] => US [patent_app_date] => 2000-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 5554 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/358/06358836.pdf [firstpage_image] =>[orig_patent_app_number] => 09595823 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/595823
Wafer level package incorporating elastomeric pads in dummy plugs Jun 15, 2000 Issued
Array ( [id] => 4380670 [patent_doc_number] => 06261874 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Fast recovery diode and method for its manufacture' [patent_app_type] => 1 [patent_app_number] => 9/593333 [patent_app_country] => US [patent_app_date] => 2000-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1195 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/261/06261874.pdf [firstpage_image] =>[orig_patent_app_number] => 593333 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/593333
Fast recovery diode and method for its manufacture Jun 13, 2000 Issued
Array ( [id] => 1205532 [patent_doc_number] => 06716706 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-06 [patent_title] => 'Method and system for forming a long channel device' [patent_app_type] => B1 [patent_app_number] => 09/592124 [patent_app_country] => US [patent_app_date] => 2000-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1723 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/716/06716706.pdf [firstpage_image] =>[orig_patent_app_number] => 09592124 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/592124
Method and system for forming a long channel device Jun 11, 2000 Issued
Array ( [id] => 4378171 [patent_doc_number] => 06303476 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Thermally induced reflectivity switch for laser thermal processing' [patent_app_type] => 1 [patent_app_number] => 9/592184 [patent_app_country] => US [patent_app_date] => 2000-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4418 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/303/06303476.pdf [firstpage_image] =>[orig_patent_app_number] => 592184 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/592184
Thermally induced reflectivity switch for laser thermal processing Jun 11, 2000 Issued
Array ( [id] => 4343679 [patent_doc_number] => 06284580 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Method for manufacturing a MOS transistor having multi-layered gate oxide' [patent_app_type] => 1 [patent_app_number] => 9/590013 [patent_app_country] => US [patent_app_date] => 2000-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 23 [patent_no_of_words] => 5643 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/284/06284580.pdf [firstpage_image] =>[orig_patent_app_number] => 590013 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/590013
Method for manufacturing a MOS transistor having multi-layered gate oxide Jun 8, 2000 Issued
Array ( [id] => 1520673 [patent_doc_number] => 06413824 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'METHOD TO PARTIALLY OR COMPLETELY SUPPRESS POCKET IMPLANT IN SELECTIVE CIRCUIT ELEMENTS WITH NO ADDITIONAL MASK IN A CMOS FLOW WHERE SEPARATE MASKING STEPS ARE USED FOR THE DRAIN EXTENSION IMPLANTS FOR THE LOW VOLTAGE AND HIGH VOLTAGE TRANSISTORS' [patent_app_type] => B1 [patent_app_number] => 09/589953 [patent_app_country] => US [patent_app_date] => 2000-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 21 [patent_no_of_words] => 3600 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/413/06413824.pdf [firstpage_image] =>[orig_patent_app_number] => 09589953 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/589953
METHOD TO PARTIALLY OR COMPLETELY SUPPRESS POCKET IMPLANT IN SELECTIVE CIRCUIT ELEMENTS WITH NO ADDITIONAL MASK IN A CMOS FLOW WHERE SEPARATE MASKING STEPS ARE USED FOR THE DRAIN EXTENSION IMPLANTS FOR THE LOW VOLTAGE AND HIGH VOLTAGE TRANSISTORS Jun 7, 2000 Issued
Array ( [id] => 1570166 [patent_doc_number] => 06498054 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-24 [patent_title] => 'Method of underfilling a flip-chip semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/585964 [patent_app_country] => US [patent_app_date] => 2000-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 2478 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/498/06498054.pdf [firstpage_image] =>[orig_patent_app_number] => 09585964 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/585964
Method of underfilling a flip-chip semiconductor device Jun 1, 2000 Issued
Array ( [id] => 7640309 [patent_doc_number] => 06395605 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Multifunctional protective component' [patent_app_type] => B1 [patent_app_number] => 09/579153 [patent_app_country] => US [patent_app_date] => 2000-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 1688 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 13 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/395/06395605.pdf [firstpage_image] =>[orig_patent_app_number] => 09579153 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/579153
Multifunctional protective component May 24, 2000 Issued
Array ( [id] => 1401084 [patent_doc_number] => 06534336 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-18 [patent_title] => 'Production method of photoelectric conversion device, and photoelectric conversion device produced by the method' [patent_app_type] => B1 [patent_app_number] => 09/572940 [patent_app_country] => US [patent_app_date] => 2000-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 78 [patent_no_of_words] => 8641 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/534/06534336.pdf [firstpage_image] =>[orig_patent_app_number] => 09572940 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/572940
Production method of photoelectric conversion device, and photoelectric conversion device produced by the method May 17, 2000 Issued
Array ( [id] => 1561195 [patent_doc_number] => 06362088 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Method of forming ohmic conductive components in a single chamber process' [patent_app_type] => B1 [patent_app_number] => 09/571763 [patent_app_country] => US [patent_app_date] => 2000-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2515 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/362/06362088.pdf [firstpage_image] =>[orig_patent_app_number] => 09571763 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/571763
Method of forming ohmic conductive components in a single chamber process May 15, 2000 Issued
Array ( [id] => 1332361 [patent_doc_number] => 06596603 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-22 [patent_title] => 'Semiconductor device and manufacturing method thereof, and registration accuracy measurement enhancement method' [patent_app_type] => B1 [patent_app_number] => 09/570463 [patent_app_country] => US [patent_app_date] => 2000-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4214 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/596/06596603.pdf [firstpage_image] =>[orig_patent_app_number] => 09570463 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/570463
Semiconductor device and manufacturing method thereof, and registration accuracy measurement enhancement method May 11, 2000 Issued
Array ( [id] => 4266308 [patent_doc_number] => 06306679 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Photodiode having transparent insulating film around gate islands above P-N junction' [patent_app_type] => 1 [patent_app_number] => 9/565913 [patent_app_country] => US [patent_app_date] => 2000-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3242 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/306/06306679.pdf [firstpage_image] =>[orig_patent_app_number] => 565913 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/565913
Photodiode having transparent insulating film around gate islands above P-N junction May 4, 2000 Issued
Array ( [id] => 4406783 [patent_doc_number] => 06238945 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Method of making P-type group III-nitride semiconductor device having improved P contact' [patent_app_type] => 1 [patent_app_number] => 9/562494 [patent_app_country] => US [patent_app_date] => 2000-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 5321 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/238/06238945.pdf [firstpage_image] =>[orig_patent_app_number] => 562494 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/562494
Method of making P-type group III-nitride semiconductor device having improved P contact Apr 30, 2000 Issued
Array ( [id] => 4266581 [patent_doc_number] => 06306698 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Semiconductor device having metal silicide regions of differing thicknesses above the gate electrode and the source/drain regions, and method of making same' [patent_app_type] => 1 [patent_app_number] => 9/558963 [patent_app_country] => US [patent_app_date] => 2000-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 4543 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/306/06306698.pdf [firstpage_image] =>[orig_patent_app_number] => 558963 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/558963
Semiconductor device having metal silicide regions of differing thicknesses above the gate electrode and the source/drain regions, and method of making same Apr 24, 2000 Issued
Array ( [id] => 4286773 [patent_doc_number] => 06268257 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Method of forming a transistor having a low-resistance gate electrode' [patent_app_type] => 1 [patent_app_number] => 9/557714 [patent_app_country] => US [patent_app_date] => 2000-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3919 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/268/06268257.pdf [firstpage_image] =>[orig_patent_app_number] => 557714 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/557714
Method of forming a transistor having a low-resistance gate electrode Apr 24, 2000 Issued
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