Search

Long Pham

Examiner (ID: 16756, Phone: (571)272-1714 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2899, 2897, 1107, 2814, 1763, 2812, 2822, 2823
Total Applications
3709
Issued Applications
3257
Pending Applications
178
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18623874 [patent_doc_number] => 11756930 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-12 [patent_title] => High bandwidth module [patent_app_type] => utility [patent_app_number] => 17/520718 [patent_app_country] => US [patent_app_date] => 2021-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 26 [patent_no_of_words] => 6433 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17520718 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/520718
High bandwidth module Nov 7, 2021 Issued
Array ( [id] => 19671000 [patent_doc_number] => 12183771 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-31 [patent_title] => Display device [patent_app_type] => utility [patent_app_number] => 17/520227 [patent_app_country] => US [patent_app_date] => 2021-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 23493 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17520227 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/520227
Display device Nov 4, 2021 Issued
Array ( [id] => 17870764 [patent_doc_number] => 20220293501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 17/453243 [patent_app_country] => US [patent_app_date] => 2021-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15217 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17453243 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/453243
Semiconductor package Nov 1, 2021 Issued
Array ( [id] => 17645441 [patent_doc_number] => 20220173180 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-02 [patent_title] => ELECTROLUMINESCENT DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/515731 [patent_app_country] => US [patent_app_date] => 2021-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15727 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17515731 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/515731
Electroluminescent display device Oct 31, 2021 Issued
Array ( [id] => 17431701 [patent_doc_number] => 20220059410 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => POWER REDUCTION IN FINFET STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/516404 [patent_app_country] => US [patent_app_date] => 2021-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8319 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17516404 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/516404
Power reduction in finFET structures Oct 31, 2021 Issued
Array ( [id] => 17582963 [patent_doc_number] => 20220139818 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => Process for Manufacturing a Chip-Card Module with Soldered Electronic Component [patent_app_type] => utility [patent_app_number] => 17/452131 [patent_app_country] => US [patent_app_date] => 2021-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4339 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17452131 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/452131
Process for manufacturing a chip-card module with soldered electronic component Oct 24, 2021 Issued
Array ( [id] => 17403079 [patent_doc_number] => 20220045170 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-10 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/509061 [patent_app_country] => US [patent_app_date] => 2021-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3205 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17509061 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/509061
Semiconductor device and method for fabricating the same Oct 23, 2021 Issued
Array ( [id] => 18320090 [patent_doc_number] => 20230118218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => PACKAGE SUBSTRATE HAVING POROUS DIELECTRIC LAYER [patent_app_type] => utility [patent_app_number] => 17/506156 [patent_app_country] => US [patent_app_date] => 2021-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5267 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17506156 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/506156
Package substrate having porous dielectric layer Oct 19, 2021 Issued
Array ( [id] => 18311946 [patent_doc_number] => 20230115846 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => Electronic Package and Method for Manufacturing an Electronic Package [patent_app_type] => utility [patent_app_number] => 17/504911 [patent_app_country] => US [patent_app_date] => 2021-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8167 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17504911 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/504911
Electronic package and method for manufacturing an electronic package Oct 18, 2021 Issued
Array ( [id] => 18983617 [patent_doc_number] => 11908806 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Semiconductor package and method of fabricating the same [patent_app_type] => utility [patent_app_number] => 17/501008 [patent_app_country] => US [patent_app_date] => 2021-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 25 [patent_no_of_words] => 9251 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17501008 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/501008
Semiconductor package and method of fabricating the same Oct 13, 2021 Issued
Array ( [id] => 17536721 [patent_doc_number] => 20220115330 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => ELECTRONIC SYSTEM IN PACKAGE COMPRISING PROTECTED SIDE FACES [patent_app_type] => utility [patent_app_number] => 17/450571 [patent_app_country] => US [patent_app_date] => 2021-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6443 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17450571 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/450571
Electronic system in package comprising protected side faces Oct 11, 2021 Issued
Array ( [id] => 17599410 [patent_doc_number] => 20220148984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-12 [patent_title] => DEVICES RELATED TO DUAL-SIDED MODULE WITH LAND-GRID ARRAY (LGA) FOOTPRINT [patent_app_type] => utility [patent_app_number] => 17/493720 [patent_app_country] => US [patent_app_date] => 2021-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6174 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17493720 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/493720
Devices related to dual-sided module with land-grid array (LGA) footprint Oct 3, 2021 Issued
Array ( [id] => 19063137 [patent_doc_number] => 11942387 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-26 [patent_title] => Plated walls defining mold compound cavities [patent_app_type] => utility [patent_app_number] => 17/491354 [patent_app_country] => US [patent_app_date] => 2021-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 45 [patent_no_of_words] => 3789 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17491354 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/491354
Plated walls defining mold compound cavities Sep 29, 2021 Issued
Array ( [id] => 18281231 [patent_doc_number] => 20230096703 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => ELECTRONIC PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/491220 [patent_app_country] => US [patent_app_date] => 2021-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8021 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17491220 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/491220
Electronic package structure and method of manufacturing the same Sep 29, 2021 Issued
Array ( [id] => 19796302 [patent_doc_number] => 12237271 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-25 [patent_title] => Module and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/488888 [patent_app_country] => US [patent_app_date] => 2021-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3885 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17488888 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/488888
Module and method of manufacturing the same Sep 28, 2021 Issued
Array ( [id] => 18271631 [patent_doc_number] => 20230092873 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => SEMICONDUCTOR DEVICE PACKAGE [patent_app_type] => utility [patent_app_number] => 17/483720 [patent_app_country] => US [patent_app_date] => 2021-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10372 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17483720 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/483720
Semiconductor device package Sep 22, 2021 Issued
Array ( [id] => 17339455 [patent_doc_number] => 20220005786 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-06 [patent_title] => METHOD FOR FABRICATING ELECTRONIC PACKAGE [patent_app_type] => utility [patent_app_number] => 17/481610 [patent_app_country] => US [patent_app_date] => 2021-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4978 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17481610 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/481610
Method for fabricating electronic package Sep 21, 2021 Issued
Array ( [id] => 18983541 [patent_doc_number] => 11908729 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Selective etches for reducing cone formation in shallow trench isolations [patent_app_type] => utility [patent_app_number] => 17/478306 [patent_app_country] => US [patent_app_date] => 2021-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 6332 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17478306 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/478306
Selective etches for reducing cone formation in shallow trench isolations Sep 16, 2021 Issued
Array ( [id] => 18759910 [patent_doc_number] => 11810950 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-07 [patent_title] => Semiconductor structure [patent_app_type] => utility [patent_app_number] => 17/447673 [patent_app_country] => US [patent_app_date] => 2021-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 20 [patent_no_of_words] => 6356 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17447673 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/447673
Semiconductor structure Sep 13, 2021 Issued
Array ( [id] => 18243837 [patent_doc_number] => 20230076148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => SILICON NITRIDE LINER FOR PROMOTION OF MOLD ADHESION IN INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 17/470404 [patent_app_country] => US [patent_app_date] => 2021-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17127 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17470404 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/470404
SILICON NITRIDE LINER FOR PROMOTION OF MOLD ADHESION IN INTEGRATED CIRCUITS Sep 8, 2021 Pending
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