Long Pham

Array ( [id] => 4358403 [patent_doc_number] => 06255182 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Method of forming a gate structure of a transistor by means of scalable spacer technology' [patent_app_type] => 1 [patent_app_number] => 9/503634 [patent_app_country] => US [patent_app_date] => 2000-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 3521 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/255/06255182.pdf [firstpage_image] =>[orig_patent_app_number] => 503634 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4356657 [patent_doc_number] => 06174748 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Method of forming a tapered section in a semiconductor device to provide for reproducible mode profile of the output beam' [patent_app_type] => 1 [patent_app_number] => 9/502154 [patent_app_country] => US [patent_app_date] => 2000-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 25 [patent_no_of_words] => 8128 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/174/06174748.pdf [firstpage_image] =>[orig_patent_app_number] => 502154 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4259291 [patent_doc_number] => 06258697 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Method of etching contacts with reduced oxide stress' [patent_app_type] => 1 [patent_app_number] => 9/502333 [patent_app_country] => US [patent_app_date] => 2000-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 3150 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/258/06258697.pdf [firstpage_image] =>[orig_patent_app_number] => 502333 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4394737 [patent_doc_number] => 06297104 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Methods to produce asymmetric MOSFET devices' [patent_app_type] => 1 [patent_app_number] => 9/496833 [patent_app_country] => US [patent_app_date] => 2000-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 3484 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/297/06297104.pdf [firstpage_image] =>[orig_patent_app_number] => 496833 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4347907 [patent_doc_number] => 06214681 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Process for forming polysilicon/germanium thin films without germanium outgassing' [patent_app_type] => 1 [patent_app_number] => 9/491843 [patent_app_country] => US [patent_app_date] => 2000-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 23 [patent_no_of_words] => 6037 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/214/06214681.pdf [firstpage_image] =>[orig_patent_app_number] => 491843 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4354969 [patent_doc_number] => 06200887 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Method to form a smooth gate polysilicon sidewall in the fabrication of integrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/490133 [patent_app_country] => US [patent_app_date] => 2000-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1576 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/200/06200887.pdf [firstpage_image] =>[orig_patent_app_number] => 490133 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1297205 [patent_doc_number] => 06627475 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-30 [patent_title] => 'Buried photodiode structure for CMOS image sensor' [patent_app_type] => B1 [patent_app_number] => 09/483034 [patent_app_country] => US [patent_app_date] => 2000-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2009 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/627/06627475.pdf [firstpage_image] =>[orig_patent_app_number] => 09483034 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4417275 [patent_doc_number] => 06194286 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Method of etching thermally grown oxide substantially selectively relative to deposited oxide' [patent_app_type] => 1 [patent_app_number] => 9/483746 [patent_app_country] => US [patent_app_date] => 2000-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 1667 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/194/06194286.pdf [firstpage_image] =>[orig_patent_app_number] => 483746 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4258148 [patent_doc_number] => 06258618 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Light emitting device having a finely-patterned reflective contact' [patent_app_type] => 1 [patent_app_number] => 9/483293 [patent_app_country] => US [patent_app_date] => 2000-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2563 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/258/06258618.pdf [firstpage_image] =>[orig_patent_app_number] => 483293 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4294393 [patent_doc_number] => 06184116 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Method to fabricate the MOS gate' [patent_app_type] => 1 [patent_app_number] => 9/480264 [patent_app_country] => US [patent_app_date] => 2000-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 2743 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/184/06184116.pdf [firstpage_image] =>[orig_patent_app_number] => 480264 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4289945 [patent_doc_number] => 06235607 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Method for establishing component isolation regions in SOI semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/479493 [patent_app_country] => US [patent_app_date] => 2000-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1528 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/235/06235607.pdf [firstpage_image] =>[orig_patent_app_number] => 479493 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4322231 [patent_doc_number] => 06331494 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-18 [patent_title] => 'Deposition of low dielectric constant thin film without use of an oxidizer' [patent_app_type] => 1 [patent_app_number] => 9/474844 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 7489 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/331/06331494.pdf [firstpage_image] =>[orig_patent_app_number] => 474844 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4347878 [patent_doc_number] => 06214679 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Cobalt salicidation method on a silicon germanium film' [patent_app_type] => 1 [patent_app_number] => 9/476393 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5331 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/214/06214679.pdf [firstpage_image] =>[orig_patent_app_number] => 476393 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1553407 [patent_doc_number] => 06348361 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-19 [patent_title] => 'CMOS image sensor having enhanced photosensitivity and method for fabricating the same' [patent_app_type] => B1 [patent_app_number] => 09/476423 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2218 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/348/06348361.pdf [firstpage_image] =>[orig_patent_app_number] => 09476423 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1553545 [patent_doc_number] => 06348392 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-19 [patent_title] => 'Resistor and method of manufacturing the same' [patent_app_type] => B1 [patent_app_number] => 09/403184 [patent_app_country] => US [patent_app_date] => 1999-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 35 [patent_no_of_words] => 5146 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/348/06348392.pdf [firstpage_image] =>[orig_patent_app_number] => 09403184 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4344139 [patent_doc_number] => 06284611 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Method for salicide process using a titanium nitride barrier layer' [patent_app_type] => 1 [patent_app_number] => 9/467134 [patent_app_country] => US [patent_app_date] => 1999-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 1997 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/284/06284611.pdf [firstpage_image] =>[orig_patent_app_number] => 467134 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4380889 [patent_doc_number] => 06261888 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Method of forming CMOS integrated circuitry' [patent_app_type] => 1 [patent_app_number] => 9/468281 [patent_app_country] => US [patent_app_date] => 1999-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2487 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/261/06261888.pdf [firstpage_image] =>[orig_patent_app_number] => 468281 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1462569 [patent_doc_number] => 06350670 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'Method for making a semiconductor device having a carbon doped oxide insulating layer' [patent_app_type] => B1 [patent_app_number] => 09/465654 [patent_app_country] => US [patent_app_date] => 1999-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 2537 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/350/06350670.pdf [firstpage_image] =>[orig_patent_app_number] => 09465654 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4409020 [patent_doc_number] => 06228745 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Selective reduction of sidewall slope on isolation edge' [patent_app_type] => 1 [patent_app_number] => 9/460134 [patent_app_country] => US [patent_app_date] => 1999-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 6166 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/228/06228745.pdf [firstpage_image] =>[orig_patent_app_number] => 460134 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4153131 [patent_doc_number] => 06107147 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Stacked poly/amorphous silicon gate giving low sheet resistance silicide film at submicron linewidths' [patent_app_type] => 1 [patent_app_number] => 9/453374 [patent_app_country] => US [patent_app_date] => 1999-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 1959 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/107/06107147.pdf [firstpage_image] =>[orig_patent_app_number] => 453374 [rel_patent_id] =>[rel_patent_doc_number] =>)