Search

Long Pham

Examiner (ID: 5269, Phone: (571)272-1714 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2822, 2899, 2897, 2823, 1107, 2814, 2812, 1763
Total Applications
3774
Issued Applications
3306
Pending Applications
160
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3910976 [patent_doc_number] => 06001707 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Method for forming shallow trench isolation structure' [patent_app_type] => 1 [patent_app_number] => 9/241760 [patent_app_country] => US [patent_app_date] => 1999-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 2732 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/001/06001707.pdf [firstpage_image] =>[orig_patent_app_number] => 241760 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/241760
Method for forming shallow trench isolation structure Jan 31, 1999 Issued
Array ( [id] => 3976472 [patent_doc_number] => 05937309 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Method for fabricating shallow trench isolation structure' [patent_app_type] => 1 [patent_app_number] => 9/241977 [patent_app_country] => US [patent_app_date] => 1999-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1868 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/937/05937309.pdf [firstpage_image] =>[orig_patent_app_number] => 241977 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/241977
Method for fabricating shallow trench isolation structure Jan 31, 1999 Issued
Array ( [id] => 4395093 [patent_doc_number] => 06297128 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Process for manufacturing shallow trenches filled with dielectric material having low mechanical stress' [patent_app_type] => 1 [patent_app_number] => 9/240560 [patent_app_country] => US [patent_app_date] => 1999-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3705 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/297/06297128.pdf [firstpage_image] =>[orig_patent_app_number] => 240560 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/240560
Process for manufacturing shallow trenches filled with dielectric material having low mechanical stress Jan 28, 1999 Issued
Array ( [id] => 3944330 [patent_doc_number] => 05998273 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Fabrication of semiconductor device having shallow junctions' [patent_app_type] => 1 [patent_app_number] => 9/236690 [patent_app_country] => US [patent_app_date] => 1999-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 1953 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/998/05998273.pdf [firstpage_image] =>[orig_patent_app_number] => 236690 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/236690
Fabrication of semiconductor device having shallow junctions Jan 24, 1999 Issued
Array ( [id] => 4292446 [patent_doc_number] => 06180492 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Method of forming a liner for shallow trench isolation' [patent_app_type] => 1 [patent_app_number] => 9/237298 [patent_app_country] => US [patent_app_date] => 1999-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 1558 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/180/06180492.pdf [firstpage_image] =>[orig_patent_app_number] => 237298 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/237298
Method of forming a liner for shallow trench isolation Jan 24, 1999 Issued
Array ( [id] => 4188492 [patent_doc_number] => 06153488 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Method for producing semiconductor device, and semiconductor device produced by same' [patent_app_type] => 1 [patent_app_number] => 9/229887 [patent_app_country] => US [patent_app_date] => 1999-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 31 [patent_no_of_words] => 7143 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/153/06153488.pdf [firstpage_image] =>[orig_patent_app_number] => 229887 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/229887
Method for producing semiconductor device, and semiconductor device produced by same Jan 13, 1999 Issued
Array ( [id] => 3943740 [patent_doc_number] => 05998232 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Planar technology for producing light-emitting devices' [patent_app_type] => 1 [patent_app_number] => 9/231689 [patent_app_country] => US [patent_app_date] => 1999-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 6709 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/998/05998232.pdf [firstpage_image] =>[orig_patent_app_number] => 231689 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/231689
Planar technology for producing light-emitting devices Jan 13, 1999 Issued
Array ( [id] => 4101938 [patent_doc_number] => 06100163 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Gap filling of shallow trench isolation by ozone-tetraethoxysilane' [patent_app_type] => 1 [patent_app_number] => 9/226277 [patent_app_country] => US [patent_app_date] => 1999-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 7051 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/100/06100163.pdf [firstpage_image] =>[orig_patent_app_number] => 226277 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/226277
Gap filling of shallow trench isolation by ozone-tetraethoxysilane Jan 6, 1999 Issued
Array ( [id] => 4249882 [patent_doc_number] => 06207514 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Method for forming borderless gate structures and apparatus formed thereby' [patent_app_type] => 1 [patent_app_number] => 9/224760 [patent_app_country] => US [patent_app_date] => 1999-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 5294 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/207/06207514.pdf [firstpage_image] =>[orig_patent_app_number] => 224760 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/224760
Method for forming borderless gate structures and apparatus formed thereby Jan 3, 1999 Issued
Array ( [id] => 4178000 [patent_doc_number] => 06037238 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Process to reduce defect formation occurring during shallow trench isolation formation' [patent_app_type] => 1 [patent_app_number] => 9/224717 [patent_app_country] => US [patent_app_date] => 1999-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2647 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/037/06037238.pdf [firstpage_image] =>[orig_patent_app_number] => 224717 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/224717
Process to reduce defect formation occurring during shallow trench isolation formation Jan 3, 1999 Issued
Array ( [id] => 4141879 [patent_doc_number] => 06030882 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Method for manufacturing shallow trench isolation structure' [patent_app_type] => 1 [patent_app_number] => 9/223200 [patent_app_country] => US [patent_app_date] => 1998-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 2353 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 13 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/030/06030882.pdf [firstpage_image] =>[orig_patent_app_number] => 223200 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/223200
Method for manufacturing shallow trench isolation structure Dec 29, 1998 Issued
Array ( [id] => 3999577 [patent_doc_number] => 05950093 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Method for aligning shallow trench isolation' [patent_app_type] => 1 [patent_app_number] => 9/223327 [patent_app_country] => US [patent_app_date] => 1998-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 1791 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/950/05950093.pdf [firstpage_image] =>[orig_patent_app_number] => 223327 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/223327
Method for aligning shallow trench isolation Dec 29, 1998 Issued
Array ( [id] => 3942221 [patent_doc_number] => 05946574 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Method for forming a diode protection circuit connecting to MOS device' [patent_app_type] => 1 [patent_app_number] => 9/218540 [patent_app_country] => US [patent_app_date] => 1998-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 2237 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/946/05946574.pdf [firstpage_image] =>[orig_patent_app_number] => 218540 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/218540
Method for forming a diode protection circuit connecting to MOS device Dec 21, 1998 Issued
Array ( [id] => 4293591 [patent_doc_number] => 06197640 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Semiconductor component and method of manufacture' [patent_app_type] => 1 [patent_app_number] => 9/217120 [patent_app_country] => US [patent_app_date] => 1998-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4607 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/197/06197640.pdf [firstpage_image] =>[orig_patent_app_number] => 217120 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/217120
Semiconductor component and method of manufacture Dec 20, 1998 Issued
Array ( [id] => 4357199 [patent_doc_number] => 06190973 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Method of fabricating a high quality thin oxide' [patent_app_type] => 1 [patent_app_number] => 9/215797 [patent_app_country] => US [patent_app_date] => 1998-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3527 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/190/06190973.pdf [firstpage_image] =>[orig_patent_app_number] => 215797 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/215797
Method of fabricating a high quality thin oxide Dec 17, 1998 Issued
Array ( [id] => 4366230 [patent_doc_number] => 06274449 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Method of pocket implant modeling for a CMOS process' [patent_app_type] => 1 [patent_app_number] => 9/216300 [patent_app_country] => US [patent_app_date] => 1998-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3066 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/274/06274449.pdf [firstpage_image] =>[orig_patent_app_number] => 216300 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/216300
Method of pocket implant modeling for a CMOS process Dec 17, 1998 Issued
09/212553 AMORPHIZATION OF SUBSTRATE TO PREVENT SILICIDE ENCROACHMENT INTO CHANNEL REGION OF FIELD EFFECT TRANSISTOR Dec 15, 1998 Abandoned
Array ( [id] => 3941833 [patent_doc_number] => 05989979 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Method for controlling the silicon nitride profile during patterning using a novel plasma etch process' [patent_app_type] => 1 [patent_app_number] => 9/208920 [patent_app_country] => US [patent_app_date] => 1998-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3262 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/989/05989979.pdf [firstpage_image] =>[orig_patent_app_number] => 208920 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/208920
Method for controlling the silicon nitride profile during patterning using a novel plasma etch process Dec 9, 1998 Issued
Array ( [id] => 4405230 [patent_doc_number] => 06232165 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Buried guard rings and method for forming the same' [patent_app_type] => 1 [patent_app_number] => 9/207630 [patent_app_country] => US [patent_app_date] => 1998-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3105 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/232/06232165.pdf [firstpage_image] =>[orig_patent_app_number] => 207630 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/207630
Buried guard rings and method for forming the same Dec 8, 1998 Issued
Array ( [id] => 4293416 [patent_doc_number] => 06184050 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Method for forming a photodiode' [patent_app_type] => 1 [patent_app_number] => 9/206857 [patent_app_country] => US [patent_app_date] => 1998-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1700 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/184/06184050.pdf [firstpage_image] =>[orig_patent_app_number] => 206857 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/206857
Method for forming a photodiode Dec 7, 1998 Issued
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