Search

Long Pham

Examiner (ID: 5269, Phone: (571)272-1714 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2822, 2899, 2897, 2823, 1107, 2814, 2812, 1763
Total Applications
3774
Issued Applications
3306
Pending Applications
160
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4145661 [patent_doc_number] => 06063671 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'Method of forming a high-voltage device' [patent_app_type] => 1 [patent_app_number] => 9/204137 [patent_app_country] => US [patent_app_date] => 1998-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2998 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/063/06063671.pdf [firstpage_image] =>[orig_patent_app_number] => 204137 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/204137
Method of forming a high-voltage device Dec 1, 1998 Issued
Array ( [id] => 4235377 [patent_doc_number] => 06165858 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Enhanced silicidation formation for high speed MOS device by junction grading with dual implant dopant species' [patent_app_type] => 1 [patent_app_number] => 9/200143 [patent_app_country] => US [patent_app_date] => 1998-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5993 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/165/06165858.pdf [firstpage_image] =>[orig_patent_app_number] => 200143 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/200143
Enhanced silicidation formation for high speed MOS device by junction grading with dual implant dopant species Nov 24, 1998 Issued
Array ( [id] => 4182238 [patent_doc_number] => 06150220 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Insulation layer structure and method for making the same' [patent_app_type] => 1 [patent_app_number] => 9/195550 [patent_app_country] => US [patent_app_date] => 1998-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 2025 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/150/06150220.pdf [firstpage_image] =>[orig_patent_app_number] => 195550 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/195550
Insulation layer structure and method for making the same Nov 18, 1998 Issued
Array ( [id] => 4405830 [patent_doc_number] => 06171912 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Method of manufacturing a semiconductor device comprising a field effect transistor' [patent_app_type] => 1 [patent_app_number] => 9/196067 [patent_app_country] => US [patent_app_date] => 1998-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 3365 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/171/06171912.pdf [firstpage_image] =>[orig_patent_app_number] => 196067 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/196067
Method of manufacturing a semiconductor device comprising a field effect transistor Nov 18, 1998 Issued
Array ( [id] => 4354867 [patent_doc_number] => 06200880 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Method for forming shallow trench isolation' [patent_app_type] => 1 [patent_app_number] => 9/192877 [patent_app_country] => US [patent_app_date] => 1998-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 1624 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/200/06200880.pdf [firstpage_image] =>[orig_patent_app_number] => 192877 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/192877
Method for forming shallow trench isolation Nov 15, 1998 Issued
Array ( [id] => 3999532 [patent_doc_number] => 05950090 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Method for fabricating a metal-oxide semiconductor transistor' [patent_app_type] => 1 [patent_app_number] => 9/193217 [patent_app_country] => US [patent_app_date] => 1998-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 4388 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/950/05950090.pdf [firstpage_image] =>[orig_patent_app_number] => 193217 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/193217
Method for fabricating a metal-oxide semiconductor transistor Nov 15, 1998 Issued
Array ( [id] => 3957123 [patent_doc_number] => 05930616 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Methods of forming a field effect transistor and method of forming CMOS circuitry' [patent_app_type] => 1 [patent_app_number] => 9/192635 [patent_app_country] => US [patent_app_date] => 1998-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2773 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930616.pdf [firstpage_image] =>[orig_patent_app_number] => 192635 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/192635
Methods of forming a field effect transistor and method of forming CMOS circuitry Nov 15, 1998 Issued
Array ( [id] => 4070313 [patent_doc_number] => 06069020 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-30 [patent_title] => 'Method of manufacturing semiconductor light-emitting device' [patent_app_type] => 1 [patent_app_number] => 9/189680 [patent_app_country] => US [patent_app_date] => 1998-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4343 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/069/06069020.pdf [firstpage_image] =>[orig_patent_app_number] => 189680 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/189680
Method of manufacturing semiconductor light-emitting device Nov 12, 1998 Issued
Array ( [id] => 4408416 [patent_doc_number] => 06265286 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Planarization of LOCOS through recessed reoxidation techniques' [patent_app_type] => 1 [patent_app_number] => 9/190747 [patent_app_country] => US [patent_app_date] => 1998-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 7 [patent_no_of_words] => 1546 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/265/06265286.pdf [firstpage_image] =>[orig_patent_app_number] => 190747 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/190747
Planarization of LOCOS through recessed reoxidation techniques Nov 11, 1998 Issued
Array ( [id] => 4292236 [patent_doc_number] => 06180476 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Dual amorphization implant process for ultra-shallow drain and source extensions' [patent_app_type] => 1 [patent_app_number] => 9/187630 [patent_app_country] => US [patent_app_date] => 1998-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2473 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/180/06180476.pdf [firstpage_image] =>[orig_patent_app_number] => 187630 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/187630
Dual amorphization implant process for ultra-shallow drain and source extensions Nov 5, 1998 Issued
Array ( [id] => 4269460 [patent_doc_number] => 06245601 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Photoelectric converter, method for driving photoelectric converter and system having photoelectric converter' [patent_app_type] => 1 [patent_app_number] => 9/185717 [patent_app_country] => US [patent_app_date] => 1998-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 45 [patent_no_of_words] => 15094 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/245/06245601.pdf [firstpage_image] =>[orig_patent_app_number] => 185717 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/185717
Photoelectric converter, method for driving photoelectric converter and system having photoelectric converter Nov 3, 1998 Issued
Array ( [id] => 4080670 [patent_doc_number] => 06054344 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'OTP (open trigger path) latchup scheme using buried-diode for sub-quarter micron transistors' [patent_app_type] => 1 [patent_app_number] => 9/182760 [patent_app_country] => US [patent_app_date] => 1998-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2930 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/054/06054344.pdf [firstpage_image] =>[orig_patent_app_number] => 182760 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/182760
OTP (open trigger path) latchup scheme using buried-diode for sub-quarter micron transistors Oct 29, 1998 Issued
Array ( [id] => 4155145 [patent_doc_number] => 06114205 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Epitaxial channel vertical MOS transistor' [patent_app_type] => 1 [patent_app_number] => 9/183040 [patent_app_country] => US [patent_app_date] => 1998-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 20 [patent_no_of_words] => 5557 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/114/06114205.pdf [firstpage_image] =>[orig_patent_app_number] => 183040 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/183040
Epitaxial channel vertical MOS transistor Oct 29, 1998 Issued
Array ( [id] => 3943709 [patent_doc_number] => 05998230 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Method for making liquid crystal display device with reduced mask steps' [patent_app_type] => 1 [patent_app_number] => 9/176787 [patent_app_country] => US [patent_app_date] => 1998-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 41 [patent_no_of_words] => 5784 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/998/05998230.pdf [firstpage_image] =>[orig_patent_app_number] => 176787 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/176787
Method for making liquid crystal display device with reduced mask steps Oct 21, 1998 Issued
Array ( [id] => 4405628 [patent_doc_number] => 06171895 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Fabrication of buried channel devices with shallow junction depth' [patent_app_type] => 1 [patent_app_number] => 9/173547 [patent_app_country] => US [patent_app_date] => 1998-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3919 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/171/06171895.pdf [firstpage_image] =>[orig_patent_app_number] => 173547 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/173547
Fabrication of buried channel devices with shallow junction depth Oct 15, 1998 Issued
Array ( [id] => 4119062 [patent_doc_number] => 06033232 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Process of fabricating photodiode integrated with MOS device' [patent_app_type] => 1 [patent_app_number] => 9/172037 [patent_app_country] => US [patent_app_date] => 1998-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 2388 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/033/06033232.pdf [firstpage_image] =>[orig_patent_app_number] => 172037 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/172037
Process of fabricating photodiode integrated with MOS device Oct 13, 1998 Issued
Array ( [id] => 4141519 [patent_doc_number] => 06030862 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Dual gate oxide formation with minimal channel dopant diffusion' [patent_app_type] => 1 [patent_app_number] => 9/170060 [patent_app_country] => US [patent_app_date] => 1998-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3384 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/030/06030862.pdf [firstpage_image] =>[orig_patent_app_number] => 170060 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/170060
Dual gate oxide formation with minimal channel dopant diffusion Oct 12, 1998 Issued
Array ( [id] => 4188239 [patent_doc_number] => 06153473 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Method of symmetrically implanted punch-through stopper for a rugged DMOS power device' [patent_app_type] => 1 [patent_app_number] => 9/170920 [patent_app_country] => US [patent_app_date] => 1998-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2051 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/153/06153473.pdf [firstpage_image] =>[orig_patent_app_number] => 170920 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/170920
Method of symmetrically implanted punch-through stopper for a rugged DMOS power device Oct 12, 1998 Issued
Array ( [id] => 4232981 [patent_doc_number] => 06117739 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Semiconductor device with layered doped regions and methods of manufacture' [patent_app_type] => 1 [patent_app_number] => 9/166000 [patent_app_country] => US [patent_app_date] => 1998-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4169 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/117/06117739.pdf [firstpage_image] =>[orig_patent_app_number] => 166000 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/166000
Semiconductor device with layered doped regions and methods of manufacture Oct 1, 1998 Issued
Array ( [id] => 4124624 [patent_doc_number] => 06127211 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Method of manufacturing transistor' [patent_app_type] => 1 [patent_app_number] => 9/162450 [patent_app_country] => US [patent_app_date] => 1998-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 25 [patent_no_of_words] => 7324 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/127/06127211.pdf [firstpage_image] =>[orig_patent_app_number] => 162450 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/162450
Method of manufacturing transistor Sep 28, 1998 Issued
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