
Long Pham
Examiner (ID: 5269, Phone: (571)272-1714 , Office: P/2814 )
| Most Active Art Unit | 2814 |
| Art Unit(s) | 2822, 2899, 2897, 2823, 1107, 2814, 2812, 1763 |
| Total Applications | 3774 |
| Issued Applications | 3306 |
| Pending Applications | 160 |
| Abandoned Applications | 335 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3941590
[patent_doc_number] => 05989962
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-23
[patent_title] => 'Semiconductor device having dual gate and method of formation'
[patent_app_type] => 1
[patent_app_number] => 9/159040
[patent_app_country] => US
[patent_app_date] => 1998-09-23
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[pdf_file] => patents/05/989/05989962.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/159040 | Semiconductor device having dual gate and method of formation | Sep 22, 1998 | Issued |
Array
(
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[patent_issue_date] => 2001-01-30
[patent_title] => 'Semiconductor device and method of fabricating the same'
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[patent_app_date] => 1998-09-18
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Array
(
[id] => 4029558
[patent_doc_number] => 05994190
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[patent_kind] => NA
[patent_issue_date] => 1999-11-30
[patent_title] => 'Semiconductor device with impurity layer as channel stopper immediately under silicon oxide film'
[patent_app_type] => 1
[patent_app_number] => 9/150710
[patent_app_country] => US
[patent_app_date] => 1998-09-10
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[patent_drawing_sheets_cnt] => 5
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[firstpage_image] =>[orig_patent_app_number] => 150710
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/150710 | Semiconductor device with impurity layer as channel stopper immediately under silicon oxide film | Sep 9, 1998 | Issued |
Array
(
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[patent_doc_number] => 06054364
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[patent_issue_date] => 2000-04-25
[patent_title] => 'Chemical mechanical polishing etch stop for trench isolation'
[patent_app_type] => 1
[patent_app_number] => 9/149700
[patent_app_country] => US
[patent_app_date] => 1998-09-08
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[patent_drawing_sheets_cnt] => 2
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[pdf_file] => patents/06/054/06054364.pdf
[firstpage_image] =>[orig_patent_app_number] => 149700
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/149700 | Chemical mechanical polishing etch stop for trench isolation | Sep 7, 1998 | Issued |
Array
(
[id] => 4185867
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[patent_kind] => NA
[patent_issue_date] => 2000-07-25
[patent_title] => 'Isolation method of semiconductor device using second pad oxide layer formed through chemical vapor deposition (CVD)'
[patent_app_type] => 1
[patent_app_number] => 9/148060
[patent_app_country] => US
[patent_app_date] => 1998-09-04
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/093/06093622.pdf
[firstpage_image] =>[orig_patent_app_number] => 148060
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/148060 | Isolation method of semiconductor device using second pad oxide layer formed through chemical vapor deposition (CVD) | Sep 3, 1998 | Issued |
Array
(
[id] => 3966840
[patent_doc_number] => 05956577
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[patent_issue_date] => 1999-09-21
[patent_title] => 'Method of manufacturing serrated gate-type or joined structure'
[patent_app_type] => 1
[patent_app_number] => 9/140760
[patent_app_country] => US
[patent_app_date] => 1998-08-26
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[firstpage_image] =>[orig_patent_app_number] => 140760
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/140760 | Method of manufacturing serrated gate-type or joined structure | Aug 25, 1998 | Issued |
Array
(
[id] => 3943622
[patent_doc_number] => 05976937
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-02
[patent_title] => 'Transistor having ultrashallow source and drain junctions with reduced gate overlap and method'
[patent_app_type] => 1
[patent_app_number] => 9/136750
[patent_app_country] => US
[patent_app_date] => 1998-08-19
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[pdf_file] => patents/05/976/05976937.pdf
[firstpage_image] =>[orig_patent_app_number] => 136750
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/136750 | Transistor having ultrashallow source and drain junctions with reduced gate overlap and method | Aug 18, 1998 | Issued |
Array
(
[id] => 4070457
[patent_doc_number] => 05970343
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-19
[patent_title] => 'Fabrication of conductivity enhanced MOS-gated semiconductor devices'
[patent_app_type] => 1
[patent_app_number] => 9/133030
[patent_app_country] => US
[patent_app_date] => 1998-08-12
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[firstpage_image] =>[orig_patent_app_number] => 133030
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/133030 | Fabrication of conductivity enhanced MOS-gated semiconductor devices | Aug 11, 1998 | Issued |
Array
(
[id] => 1446572
[patent_doc_number] => 06368922
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-09
[patent_title] => 'Internal ESD protection structure with contact diffusion'
[patent_app_type] => B1
[patent_app_number] => 09/132939
[patent_app_country] => US
[patent_app_date] => 1998-08-11
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/132939 | Internal ESD protection structure with contact diffusion | Aug 10, 1998 | Issued |
Array
(
[id] => 3941820
[patent_doc_number] => 05989978
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-23
[patent_title] => 'Shallow trench isolation of MOSFETS with reduced corner parasitic currents'
[patent_app_type] => 1
[patent_app_number] => 9/116610
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[patent_app_date] => 1998-07-16
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[firstpage_image] =>[orig_patent_app_number] => 116610
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/116610 | Shallow trench isolation of MOSFETS with reduced corner parasitic currents | Jul 15, 1998 | Issued |
Array
(
[id] => 4130106
[patent_doc_number] => 06033958
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[patent_title] => 'Method of fabricating dual voltage MOS transistors'
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[firstpage_image] =>[orig_patent_app_number] => 108107
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/108107 | Method of fabricating dual voltage MOS transistors | Jun 29, 1998 | Issued |
Array
(
[id] => 3993510
[patent_doc_number] => 05985705
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[patent_title] => 'Low threshold voltage MOS transistor and method of manufacture'
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Array
(
[id] => 4094775
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[patent_title] => 'Method for poly-buffered locos without pitting formation'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/105337 | Method for poly-buffered locos without pitting formation | Jun 25, 1998 | Issued |
Array
(
[id] => 4004280
[patent_doc_number] => 05960289
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[patent_issue_date] => 1999-09-28
[patent_title] => 'Method for making a dual-thickness gate oxide layer using a nitride/oxide composite region'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/102267 | Method for making a dual-thickness gate oxide layer using a nitride/oxide composite region | Jun 21, 1998 | Issued |
| 09/098397 | METHOD FOR FABRICATING A HIGH BIAS METAL OXIDE SEMICONDUCTOR DEVICE | Jun 16, 1998 | Issued |
Array
(
[id] => 4002860
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/097880 | Method of forming CMOS integrated circuitry | Jun 14, 1998 | Issued |
Array
(
[id] => 4270541
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[patent_issue_date] => 2001-11-27
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[firstpage_image] =>[orig_patent_app_number] => 095884
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/095884 | Compound semiconductor light emitting device and method of fabricating the same | Jun 10, 1998 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/089624 | Semiconductor light emitting element and its manufacturing method | Jun 2, 1998 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/088440 | Method for making sub-quarter-micron MOSFET | Jun 1, 1998 | Issued |
Array
(
[id] => 4155330
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/080627 | Texturized polycrystalline silicon to aid field oxide formation | May 17, 1998 | Issued |