Search

Long Pham

Examiner (ID: 5269, Phone: (571)272-1714 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2822, 2899, 2897, 2823, 1107, 2814, 2812, 1763
Total Applications
3774
Issued Applications
3306
Pending Applications
160
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3941590 [patent_doc_number] => 05989962 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Semiconductor device having dual gate and method of formation' [patent_app_type] => 1 [patent_app_number] => 9/159040 [patent_app_country] => US [patent_app_date] => 1998-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 12 [patent_no_of_words] => 2399 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/989/05989962.pdf [firstpage_image] =>[orig_patent_app_number] => 159040 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/159040
Semiconductor device having dual gate and method of formation Sep 22, 1998 Issued
Array ( [id] => 4291746 [patent_doc_number] => 06180443 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Semiconductor device and method of fabricating the same' [patent_app_type] => 1 [patent_app_number] => 9/156777 [patent_app_country] => US [patent_app_date] => 1998-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 3802 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/180/06180443.pdf [firstpage_image] =>[orig_patent_app_number] => 156777 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/156777
Semiconductor device and method of fabricating the same Sep 17, 1998 Issued
Array ( [id] => 4029558 [patent_doc_number] => 05994190 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Semiconductor device with impurity layer as channel stopper immediately under silicon oxide film' [patent_app_type] => 1 [patent_app_number] => 9/150710 [patent_app_country] => US [patent_app_date] => 1998-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 3363 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/994/05994190.pdf [firstpage_image] =>[orig_patent_app_number] => 150710 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/150710
Semiconductor device with impurity layer as channel stopper immediately under silicon oxide film Sep 9, 1998 Issued
Array ( [id] => 4080956 [patent_doc_number] => 06054364 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'Chemical mechanical polishing etch stop for trench isolation' [patent_app_type] => 1 [patent_app_number] => 9/149700 [patent_app_country] => US [patent_app_date] => 1998-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2143 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/054/06054364.pdf [firstpage_image] =>[orig_patent_app_number] => 149700 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/149700
Chemical mechanical polishing etch stop for trench isolation Sep 7, 1998 Issued
Array ( [id] => 4185867 [patent_doc_number] => 06093622 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Isolation method of semiconductor device using second pad oxide layer formed through chemical vapor deposition (CVD)' [patent_app_type] => 1 [patent_app_number] => 9/148060 [patent_app_country] => US [patent_app_date] => 1998-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 21 [patent_no_of_words] => 2292 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/093/06093622.pdf [firstpage_image] =>[orig_patent_app_number] => 148060 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/148060
Isolation method of semiconductor device using second pad oxide layer formed through chemical vapor deposition (CVD) Sep 3, 1998 Issued
Array ( [id] => 3966840 [patent_doc_number] => 05956577 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Method of manufacturing serrated gate-type or joined structure' [patent_app_type] => 1 [patent_app_number] => 9/140760 [patent_app_country] => US [patent_app_date] => 1998-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 20 [patent_no_of_words] => 5779 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/956/05956577.pdf [firstpage_image] =>[orig_patent_app_number] => 140760 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/140760
Method of manufacturing serrated gate-type or joined structure Aug 25, 1998 Issued
Array ( [id] => 3943622 [patent_doc_number] => 05976937 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Transistor having ultrashallow source and drain junctions with reduced gate overlap and method' [patent_app_type] => 1 [patent_app_number] => 9/136750 [patent_app_country] => US [patent_app_date] => 1998-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 5938 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 334 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/976/05976937.pdf [firstpage_image] =>[orig_patent_app_number] => 136750 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/136750
Transistor having ultrashallow source and drain junctions with reduced gate overlap and method Aug 18, 1998 Issued
Array ( [id] => 4070457 [patent_doc_number] => 05970343 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Fabrication of conductivity enhanced MOS-gated semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 9/133030 [patent_app_country] => US [patent_app_date] => 1998-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 4404 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/970/05970343.pdf [firstpage_image] =>[orig_patent_app_number] => 133030 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/133030
Fabrication of conductivity enhanced MOS-gated semiconductor devices Aug 11, 1998 Issued
Array ( [id] => 1446572 [patent_doc_number] => 06368922 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Internal ESD protection structure with contact diffusion' [patent_app_type] => B1 [patent_app_number] => 09/132939 [patent_app_country] => US [patent_app_date] => 1998-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 3808 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/368/06368922.pdf [firstpage_image] =>[orig_patent_app_number] => 09132939 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/132939
Internal ESD protection structure with contact diffusion Aug 10, 1998 Issued
Array ( [id] => 3941820 [patent_doc_number] => 05989978 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Shallow trench isolation of MOSFETS with reduced corner parasitic currents' [patent_app_type] => 1 [patent_app_number] => 9/116610 [patent_app_country] => US [patent_app_date] => 1998-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 19 [patent_no_of_words] => 5428 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/989/05989978.pdf [firstpage_image] =>[orig_patent_app_number] => 116610 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/116610
Shallow trench isolation of MOSFETS with reduced corner parasitic currents Jul 15, 1998 Issued
Array ( [id] => 4130106 [patent_doc_number] => 06033958 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Method of fabricating dual voltage MOS transistors' [patent_app_type] => 1 [patent_app_number] => 9/108107 [patent_app_country] => US [patent_app_date] => 1998-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 1873 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/033/06033958.pdf [firstpage_image] =>[orig_patent_app_number] => 108107 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/108107
Method of fabricating dual voltage MOS transistors Jun 29, 1998 Issued
Array ( [id] => 3993510 [patent_doc_number] => 05985705 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Low threshold voltage MOS transistor and method of manufacture' [patent_app_type] => 1 [patent_app_number] => 9/107767 [patent_app_country] => US [patent_app_date] => 1998-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3644 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/985/05985705.pdf [firstpage_image] =>[orig_patent_app_number] => 107767 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/107767
Low threshold voltage MOS transistor and method of manufacture Jun 29, 1998 Issued
Array ( [id] => 4094775 [patent_doc_number] => 06096613 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Method for poly-buffered locos without pitting formation' [patent_app_type] => 1 [patent_app_number] => 9/105337 [patent_app_country] => US [patent_app_date] => 1998-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2455 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/096/06096613.pdf [firstpage_image] =>[orig_patent_app_number] => 105337 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/105337
Method for poly-buffered locos without pitting formation Jun 25, 1998 Issued
Array ( [id] => 4004280 [patent_doc_number] => 05960289 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Method for making a dual-thickness gate oxide layer using a nitride/oxide composite region' [patent_app_type] => 1 [patent_app_number] => 9/102267 [patent_app_country] => US [patent_app_date] => 1998-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 3969 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/960/05960289.pdf [firstpage_image] =>[orig_patent_app_number] => 102267 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/102267
Method for making a dual-thickness gate oxide layer using a nitride/oxide composite region Jun 21, 1998 Issued
09/098397 METHOD FOR FABRICATING A HIGH BIAS METAL OXIDE SEMICONDUCTOR DEVICE Jun 16, 1998 Issued
Array ( [id] => 4002860 [patent_doc_number] => 06004854 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-21 [patent_title] => 'Method of forming CMOS integrated circuitry' [patent_app_type] => 1 [patent_app_number] => 9/097880 [patent_app_country] => US [patent_app_date] => 1998-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2487 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/004/06004854.pdf [firstpage_image] =>[orig_patent_app_number] => 097880 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/097880
Method of forming CMOS integrated circuitry Jun 14, 1998 Issued
Array ( [id] => 4270541 [patent_doc_number] => 06323052 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Compound semiconductor light emitting device and method of fabricating the same' [patent_app_type] => 1 [patent_app_number] => 9/095884 [patent_app_country] => US [patent_app_date] => 1998-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 25 [patent_no_of_words] => 18595 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/323/06323052.pdf [firstpage_image] =>[orig_patent_app_number] => 095884 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/095884
Compound semiconductor light emitting device and method of fabricating the same Jun 10, 1998 Issued
Array ( [id] => 4404865 [patent_doc_number] => 06232137 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Semiconductor light emitting element and its manufacturing method' [patent_app_type] => 1 [patent_app_number] => 9/089624 [patent_app_country] => US [patent_app_date] => 1998-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 6582 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/232/06232137.pdf [firstpage_image] =>[orig_patent_app_number] => 089624 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/089624
Semiconductor light emitting element and its manufacturing method Jun 2, 1998 Issued
Array ( [id] => 3976273 [patent_doc_number] => 05937297 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Method for making sub-quarter-micron MOSFET' [patent_app_type] => 1 [patent_app_number] => 9/088440 [patent_app_country] => US [patent_app_date] => 1998-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2285 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/937/05937297.pdf [firstpage_image] =>[orig_patent_app_number] => 088440 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/088440
Method for making sub-quarter-micron MOSFET Jun 1, 1998 Issued
Array ( [id] => 4155330 [patent_doc_number] => 06114218 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Texturized polycrystalline silicon to aid field oxide formation' [patent_app_type] => 1 [patent_app_number] => 9/080627 [patent_app_country] => US [patent_app_date] => 1998-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1681 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/114/06114218.pdf [firstpage_image] =>[orig_patent_app_number] => 080627 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/080627
Texturized polycrystalline silicon to aid field oxide formation May 17, 1998 Issued
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