Search

Long Pham

Examiner (ID: 5269, Phone: (571)272-1714 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2822, 2899, 2897, 2823, 1107, 2814, 2812, 1763
Total Applications
3774
Issued Applications
3306
Pending Applications
160
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4085599 [patent_doc_number] => 06017797 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-25 [patent_title] => 'Method of fabricating a semiconductor device including complementary MOSFET and power MOSFET' [patent_app_type] => 1 [patent_app_number] => 9/075821 [patent_app_country] => US [patent_app_date] => 1998-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 6528 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/017/06017797.pdf [firstpage_image] =>[orig_patent_app_number] => 075821 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/075821
Method of fabricating a semiconductor device including complementary MOSFET and power MOSFET May 11, 1998 Issued
Array ( [id] => 4029616 [patent_doc_number] => 05994194 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Self-aligned base ohmic metal for an HBT device cross-reference to related applications' [patent_app_type] => 1 [patent_app_number] => 9/074199 [patent_app_country] => US [patent_app_date] => 1998-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 22 [patent_no_of_words] => 4215 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/994/05994194.pdf [firstpage_image] =>[orig_patent_app_number] => 074199 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/074199
Self-aligned base ohmic metal for an HBT device cross-reference to related applications May 6, 1998 Issued
Array ( [id] => 3969116 [patent_doc_number] => 05904536 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-18 [patent_title] => 'Self aligned poly emitter bipolar technology using damascene technique' [patent_app_type] => 1 [patent_app_number] => 9/071241 [patent_app_country] => US [patent_app_date] => 1998-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 2259 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/904/05904536.pdf [firstpage_image] =>[orig_patent_app_number] => 071241 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/071241
Self aligned poly emitter bipolar technology using damascene technique Apr 30, 1998 Issued
Array ( [id] => 4177935 [patent_doc_number] => 06037233 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Metal-encapsulated polysilicon gate and interconnect' [patent_app_type] => 1 [patent_app_number] => 9/069027 [patent_app_country] => US [patent_app_date] => 1998-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 11 [patent_no_of_words] => 2930 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/037/06037233.pdf [firstpage_image] =>[orig_patent_app_number] => 069027 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/069027
Metal-encapsulated polysilicon gate and interconnect Apr 26, 1998 Issued
Array ( [id] => 4136279 [patent_doc_number] => 06015719 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-18 [patent_title] => 'Transparent substrate light emitting diodes with directed light output' [patent_app_type] => 1 [patent_app_number] => 9/066089 [patent_app_country] => US [patent_app_date] => 1998-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 3847 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/015/06015719.pdf [firstpage_image] =>[orig_patent_app_number] => 066089 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/066089
Transparent substrate light emitting diodes with directed light output Apr 23, 1998 Issued
Array ( [id] => 4057892 [patent_doc_number] => 05909623 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-01 [patent_title] => 'Manufacturing method of semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/063382 [patent_app_country] => US [patent_app_date] => 1998-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 17 [patent_no_of_words] => 2750 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/909/05909623.pdf [firstpage_image] =>[orig_patent_app_number] => 063382 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/063382
Manufacturing method of semiconductor device Apr 20, 1998 Issued
Array ( [id] => 3944545 [patent_doc_number] => 05998288 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Ultra thin spacers formed laterally adjacent a gate conductor recessed below the upper surface of a substrate' [patent_app_type] => 1 [patent_app_number] => 9/062095 [patent_app_country] => US [patent_app_date] => 1998-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 26 [patent_no_of_words] => 7227 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/998/05998288.pdf [firstpage_image] =>[orig_patent_app_number] => 062095 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/062095
Ultra thin spacers formed laterally adjacent a gate conductor recessed below the upper surface of a substrate Apr 16, 1998 Issued
Array ( [id] => 4188296 [patent_doc_number] => 06153477 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Ultra short transistor channel length formed using a gate dielectric having a relatively high dielectric constant' [patent_app_type] => 1 [patent_app_number] => 9/060430 [patent_app_country] => US [patent_app_date] => 1998-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 6525 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/153/06153477.pdf [firstpage_image] =>[orig_patent_app_number] => 060430 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/060430
Ultra short transistor channel length formed using a gate dielectric having a relatively high dielectric constant Apr 13, 1998 Issued
Array ( [id] => 4097842 [patent_doc_number] => 06048769 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'CMOS integrated circuit having PMOS and NMOS devices with different gate dielectric layers' [patent_app_type] => 1 [patent_app_number] => 9/052492 [patent_app_country] => US [patent_app_date] => 1998-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 4832 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/048/06048769.pdf [firstpage_image] =>[orig_patent_app_number] => 052492 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/052492
CMOS integrated circuit having PMOS and NMOS devices with different gate dielectric layers Mar 29, 1998 Issued
Array ( [id] => 4070596 [patent_doc_number] => 05970353 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Reduced channel length lightly doped drain transistor using a sub-amorphous large tilt angle implant to provide enhanced lateral diffusion' [patent_app_type] => 1 [patent_app_number] => 9/050730 [patent_app_country] => US [patent_app_date] => 1998-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 15 [patent_no_of_words] => 5634 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/970/05970353.pdf [firstpage_image] =>[orig_patent_app_number] => 050730 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/050730
Reduced channel length lightly doped drain transistor using a sub-amorphous large tilt angle implant to provide enhanced lateral diffusion Mar 29, 1998 Issued
Array ( [id] => 3966940 [patent_doc_number] => 05956584 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Method of making self-aligned silicide CMOS transistors' [patent_app_type] => 1 [patent_app_number] => 9/050541 [patent_app_country] => US [patent_app_date] => 1998-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2459 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/956/05956584.pdf [firstpage_image] =>[orig_patent_app_number] => 050541 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/050541
Method of making self-aligned silicide CMOS transistors Mar 29, 1998 Issued
Array ( [id] => 4234894 [patent_doc_number] => 06165825 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Semiconductor device and method for producing the same' [patent_app_type] => 1 [patent_app_number] => 9/047353 [patent_app_country] => US [patent_app_date] => 1998-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 36 [patent_no_of_words] => 10534 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 326 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/165/06165825.pdf [firstpage_image] =>[orig_patent_app_number] => 047353 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/047353
Semiconductor device and method for producing the same Mar 24, 1998 Issued
Array ( [id] => 4136397 [patent_doc_number] => 06015726 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-18 [patent_title] => 'Semiconductor device and method of producing the same' [patent_app_type] => 1 [patent_app_number] => 9/046535 [patent_app_country] => US [patent_app_date] => 1998-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 24 [patent_no_of_words] => 4682 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/015/06015726.pdf [firstpage_image] =>[orig_patent_app_number] => 046535 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/046535
Semiconductor device and method of producing the same Mar 23, 1998 Issued
Array ( [id] => 3937160 [patent_doc_number] => 05981326 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Damascene isolation of CMOS transistors' [patent_app_type] => 1 [patent_app_number] => 9/046243 [patent_app_country] => US [patent_app_date] => 1998-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 930 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 326 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/981/05981326.pdf [firstpage_image] =>[orig_patent_app_number] => 046243 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/046243
Damascene isolation of CMOS transistors Mar 22, 1998 Issued
Array ( [id] => 4181386 [patent_doc_number] => 06020246 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'Forming a self-aligned epitaxial base bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 9/042430 [patent_app_country] => US [patent_app_date] => 1998-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 5718 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/020/06020246.pdf [firstpage_image] =>[orig_patent_app_number] => 042430 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/042430
Forming a self-aligned epitaxial base bipolar transistor Mar 12, 1998 Issued
Array ( [id] => 3950786 [patent_doc_number] => 05899742 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'Manufacturing method for self-aligned local interconnects and contacts simultaneously' [patent_app_type] => 1 [patent_app_number] => 9/035347 [patent_app_country] => US [patent_app_date] => 1998-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 3271 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 324 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/899/05899742.pdf [firstpage_image] =>[orig_patent_app_number] => 035347 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/035347
Manufacturing method for self-aligned local interconnects and contacts simultaneously Mar 4, 1998 Issued
Array ( [id] => 4204803 [patent_doc_number] => 06077749 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Method of making dual channel gate oxide thickness for MOSFET transistor design' [patent_app_type] => 1 [patent_app_number] => 9/034117 [patent_app_country] => US [patent_app_date] => 1998-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 4612 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/077/06077749.pdf [firstpage_image] =>[orig_patent_app_number] => 034117 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/034117
Method of making dual channel gate oxide thickness for MOSFET transistor design Mar 2, 1998 Issued
Array ( [id] => 4301682 [patent_doc_number] => 06251718 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/011891 [patent_app_country] => US [patent_app_date] => 1998-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 85 [patent_no_of_words] => 15399 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/251/06251718.pdf [firstpage_image] =>[orig_patent_app_number] => 011891 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/011891
Method for manufacturing semiconductor device Feb 22, 1998 Issued
Array ( [id] => 3957111 [patent_doc_number] => 05930615 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Method of forming CMOS having simultaneous formation of halo regions of PMOS and part of source/drain of NMOS' [patent_app_type] => 1 [patent_app_number] => 9/024875 [patent_app_country] => US [patent_app_date] => 1998-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3697 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930615.pdf [firstpage_image] =>[orig_patent_app_number] => 024875 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/024875
Method of forming CMOS having simultaneous formation of halo regions of PMOS and part of source/drain of NMOS Feb 16, 1998 Issued
Array ( [id] => 4094366 [patent_doc_number] => 06096589 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Low and high voltage CMOS devices and process for fabricating same' [patent_app_type] => 1 [patent_app_number] => 9/022757 [patent_app_country] => US [patent_app_date] => 1998-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 4095 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/096/06096589.pdf [firstpage_image] =>[orig_patent_app_number] => 022757 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/022757
Low and high voltage CMOS devices and process for fabricating same Feb 11, 1998 Issued
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