
Long Pham
Examiner (ID: 5269, Phone: (571)272-1714 , Office: P/2814 )
| Most Active Art Unit | 2814 |
| Art Unit(s) | 2822, 2899, 2897, 2823, 1107, 2814, 2812, 1763 |
| Total Applications | 3774 |
| Issued Applications | 3306 |
| Pending Applications | 160 |
| Abandoned Applications | 335 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4085599
[patent_doc_number] => 06017797
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-01-25
[patent_title] => 'Method of fabricating a semiconductor device including complementary MOSFET and power MOSFET'
[patent_app_type] => 1
[patent_app_number] => 9/075821
[patent_app_country] => US
[patent_app_date] => 1998-05-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 11
[patent_no_of_words] => 6528
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/017/06017797.pdf
[firstpage_image] =>[orig_patent_app_number] => 075821
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/075821 | Method of fabricating a semiconductor device including complementary MOSFET and power MOSFET | May 11, 1998 | Issued |
Array
(
[id] => 4029616
[patent_doc_number] => 05994194
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-30
[patent_title] => 'Self-aligned base ohmic metal for an HBT device cross-reference to related applications'
[patent_app_type] => 1
[patent_app_number] => 9/074199
[patent_app_country] => US
[patent_app_date] => 1998-05-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[pdf_file] => patents/05/994/05994194.pdf
[firstpage_image] =>[orig_patent_app_number] => 074199
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/074199 | Self-aligned base ohmic metal for an HBT device cross-reference to related applications | May 6, 1998 | Issued |
Array
(
[id] => 3969116
[patent_doc_number] => 05904536
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-05-18
[patent_title] => 'Self aligned poly emitter bipolar technology using damascene technique'
[patent_app_type] => 1
[patent_app_number] => 9/071241
[patent_app_country] => US
[patent_app_date] => 1998-05-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[firstpage_image] =>[orig_patent_app_number] => 071241
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/071241 | Self aligned poly emitter bipolar technology using damascene technique | Apr 30, 1998 | Issued |
Array
(
[id] => 4177935
[patent_doc_number] => 06037233
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-14
[patent_title] => 'Metal-encapsulated polysilicon gate and interconnect'
[patent_app_type] => 1
[patent_app_number] => 9/069027
[patent_app_country] => US
[patent_app_date] => 1998-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[pdf_file] => patents/06/037/06037233.pdf
[firstpage_image] =>[orig_patent_app_number] => 069027
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/069027 | Metal-encapsulated polysilicon gate and interconnect | Apr 26, 1998 | Issued |
Array
(
[id] => 4136279
[patent_doc_number] => 06015719
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-01-18
[patent_title] => 'Transparent substrate light emitting diodes with directed light output'
[patent_app_type] => 1
[patent_app_number] => 9/066089
[patent_app_country] => US
[patent_app_date] => 1998-04-24
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[patent_drawing_sheets_cnt] => 13
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[pdf_file] => patents/06/015/06015719.pdf
[firstpage_image] =>[orig_patent_app_number] => 066089
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/066089 | Transparent substrate light emitting diodes with directed light output | Apr 23, 1998 | Issued |
Array
(
[id] => 4057892
[patent_doc_number] => 05909623
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-01
[patent_title] => 'Manufacturing method of semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 9/063382
[patent_app_country] => US
[patent_app_date] => 1998-04-21
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/909/05909623.pdf
[firstpage_image] =>[orig_patent_app_number] => 063382
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/063382 | Manufacturing method of semiconductor device | Apr 20, 1998 | Issued |
Array
(
[id] => 3944545
[patent_doc_number] => 05998288
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-07
[patent_title] => 'Ultra thin spacers formed laterally adjacent a gate conductor recessed below the upper surface of a substrate'
[patent_app_type] => 1
[patent_app_number] => 9/062095
[patent_app_country] => US
[patent_app_date] => 1998-04-17
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[patent_drawing_sheets_cnt] => 8
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[pdf_file] => patents/05/998/05998288.pdf
[firstpage_image] =>[orig_patent_app_number] => 062095
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/062095 | Ultra thin spacers formed laterally adjacent a gate conductor recessed below the upper surface of a substrate | Apr 16, 1998 | Issued |
Array
(
[id] => 4188296
[patent_doc_number] => 06153477
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-28
[patent_title] => 'Ultra short transistor channel length formed using a gate dielectric having a relatively high dielectric constant'
[patent_app_type] => 1
[patent_app_number] => 9/060430
[patent_app_country] => US
[patent_app_date] => 1998-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 6525
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[pdf_file] => patents/06/153/06153477.pdf
[firstpage_image] =>[orig_patent_app_number] => 060430
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/060430 | Ultra short transistor channel length formed using a gate dielectric having a relatively high dielectric constant | Apr 13, 1998 | Issued |
Array
(
[id] => 4097842
[patent_doc_number] => 06048769
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-11
[patent_title] => 'CMOS integrated circuit having PMOS and NMOS devices with different gate dielectric layers'
[patent_app_type] => 1
[patent_app_number] => 9/052492
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[patent_app_date] => 1998-03-30
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/052492 | CMOS integrated circuit having PMOS and NMOS devices with different gate dielectric layers | Mar 29, 1998 | Issued |
Array
(
[id] => 4070596
[patent_doc_number] => 05970353
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[patent_issue_date] => 1999-10-19
[patent_title] => 'Reduced channel length lightly doped drain transistor using a sub-amorphous large tilt angle implant to provide enhanced lateral diffusion'
[patent_app_type] => 1
[patent_app_number] => 9/050730
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[patent_app_date] => 1998-03-30
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[pdf_file] => patents/05/970/05970353.pdf
[firstpage_image] =>[orig_patent_app_number] => 050730
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/050730 | Reduced channel length lightly doped drain transistor using a sub-amorphous large tilt angle implant to provide enhanced lateral diffusion | Mar 29, 1998 | Issued |
Array
(
[id] => 3966940
[patent_doc_number] => 05956584
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[patent_kind] => NA
[patent_issue_date] => 1999-09-21
[patent_title] => 'Method of making self-aligned silicide CMOS transistors'
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[patent_app_number] => 9/050541
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[firstpage_image] =>[orig_patent_app_number] => 050541
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/050541 | Method of making self-aligned silicide CMOS transistors | Mar 29, 1998 | Issued |
Array
(
[id] => 4234894
[patent_doc_number] => 06165825
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[patent_issue_date] => 2000-12-26
[patent_title] => 'Semiconductor device and method for producing the same'
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Array
(
[id] => 4136397
[patent_doc_number] => 06015726
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[patent_title] => 'Semiconductor device and method of producing the same'
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Array
(
[id] => 3937160
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[patent_title] => 'Damascene isolation of CMOS transistors'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/046243 | Damascene isolation of CMOS transistors | Mar 22, 1998 | Issued |
Array
(
[id] => 4181386
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[patent_title] => 'Forming a self-aligned epitaxial base bipolar transistor'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/042430 | Forming a self-aligned epitaxial base bipolar transistor | Mar 12, 1998 | Issued |
Array
(
[id] => 3950786
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Array
(
[id] => 4204803
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/011891 | Method for manufacturing semiconductor device | Feb 22, 1998 | Issued |
Array
(
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/022757 | Low and high voltage CMOS devices and process for fabricating same | Feb 11, 1998 | Issued |